Lines Matching +full:gemini +full:- +full:enable +full:- +full:ide +full:- +full:pins
2 * Driver for the Gemini pin controller
6 * This is a group-only pin controller.
19 #include <linux/pinctrl/pinconf-generic.h>
24 #include "pinctrl-utils.h"
26 #define DRIVER_NAME "pinctrl-gemini"
29 * struct gemini_pin_conf - information about configuring a pin
41 * struct gemini_pmx - state holder for the gemini pin controller
47 * @flash_pin: whether the flash pin (extended pins for parallel
64 * struct gemini_pin_group - describes a Gemini pin group
66 * @pins: an array of discrete physical pins used in this group, taken
67 * from the driver-local pin enumeration space
68 * @num_pins: the number of pins in this group array, i.e. the number of
69 * elements in .pins so we can iterate over that array
70 * @mask: bits to clear to enable this when doing pin muxing
71 * @value: bits to set to enable this when doing pin muxing
78 const unsigned int *pins; member
85 /* Some straight-forward control registers */
95 * This register controls all Gemini pad/pin multiplexing
98 * - For the bits named *_ENABLE, once you DISABLE something, it simply cannot
101 * - For the bits named *_DISABLE, once you enable something, it cannot be
135 "IDE",
308 PINCTRL_PIN(148, "J5 IDE DA1"),
323 PINCTRL_PIN(162, "K1 IDE CS1 N"),
324 PINCTRL_PIN(163, "K2 IDE CS0 N"),
326 PINCTRL_PIN(165, "K4 IDE DA2"),
327 PINCTRL_PIN(166, "K5 IDE DA0"),
342 PINCTRL_PIN(180, "L1 IDE INTRQ"),
343 PINCTRL_PIN(181, "L2 IDE DMACK N"),
344 PINCTRL_PIN(182, "L3 IDE IORDY"),
345 PINCTRL_PIN(183, "L4 IDE DIOR N"),
346 PINCTRL_PIN(184, "L5 IDE DIOW N"),
361 PINCTRL_PIN(198, "M1 IDE DMARQ"),
362 PINCTRL_PIN(199, "M2 IDE DD15"),
363 PINCTRL_PIN(200, "M3 IDE DD0"),
364 PINCTRL_PIN(201, "M4 IDE DD14"),
365 PINCTRL_PIN(202, "M5 IDE DD1"),
380 PINCTRL_PIN(216, "N1 IDE DD13"),
381 PINCTRL_PIN(217, "N2 IDE DD2"),
382 PINCTRL_PIN(218, "N3 IDE DD12"),
383 PINCTRL_PIN(219, "N4 IDE DD3"),
384 PINCTRL_PIN(220, "N5 IDE DD11"),
399 PINCTRL_PIN(234, "P1 IDE DD4"),
400 PINCTRL_PIN(235, "P2 IDE DD10"),
401 PINCTRL_PIN(236, "P3 IDE DD5"),
402 PINCTRL_PIN(237, "P4 IDE DD9"),
418 PINCTRL_PIN(252, "R1 IDE DD6"),
419 PINCTRL_PIN(253, "R2 IDE DD8"),
420 PINCTRL_PIN(254, "R3 IDE DD7"),
421 PINCTRL_PIN(255, "R4 IDE RESET N"),
534 /* GMII, ethernet pins */
606 /* NAND flash pins */
612 /* Parallel (NOR) flash pins, D[0-15], A[16-25], CE0, CE1, RB, WE, OE, ALE */
620 * The parallel flash can be set up in a 26-bit address bus mode exposing
621 * A[0-15] (A[15] takes the place of ALE), but it has the
622 * side effect of stealing pins from GMAC1 and TVC so these blocks cannot be
629 /* The extra pins */
634 /* Serial flash pins CE0, CE1, DI, DO, CK */
640 /* The GPIO0B (1-4) pins overlap with TVC and ICE */
643 /* The GPIO0C (5-7) pins overlap with ICE */
646 /* The GPIO0D (9,10) pins overlap with UART RX/TX */
649 /* The GPIO0E (8,11-15) pins overlap with LPC, UART modem pins, SSP */
652 /* The GPIO0F (16) pins overlap with LCD */
655 /* The GPIO0G (17,18) pins overlap with NAND flash CE0, CE1 */
658 /* The GPIO0H (19,20) pins overlap with parallel flash CE0, CE1 */
661 /* The GPIO0I (21,22) pins overlap with serial flash CE0, CE1 */
664 /* The GPIO0J (23) pins overlap with all flash */
667 /* The GPIO0K (24,25) pins overlap with all flash and LCD */
670 /* The GPIO0L (26-29) pins overlap with parallel flash */
673 /* The GPIO0M (30,31) pins overlap with parallel flash and NAND flash */
676 /* The GPIO1A (0-4) pins that overlap with IDE and parallel flash */
679 /* The GPIO1B (5-10, 27) pins overlap with just IDE */
684 /* The GPIO1C (11-26) pins overlap with IDE, parallel flash and NAND flash */
690 /* The GPIO1D (28-31) pins overlap with LCD and TVC */
693 /* The GPIO2A (0-3) pins overlap with GMII GMAC1 and extended parallel flash */
696 /* The GPIO2B (4-7) pins overlap with GMII GMAC1, extended parallel flash and LCD */
699 /* The GPIO2C (8-31) pins overlap with PCI */
709 .pins = gnd_3512_pins,
714 .pins = dram_3512_pins,
720 .pins = rtc_3512_pins,
725 .pins = power_3512_pins,
730 .pins = system_3512_pins,
735 .pins = vcontrol_3512_pins,
740 .pins = ice_3512_pins,
746 .pins = ide_3512_pins,
755 .pins = sata_3512_pins,
760 .pins = usb_3512_pins,
765 .pins = gmii_gmac0_3512_pins,
771 .pins = gmii_gmac1_3512_pins,
773 /* Bring out RGMII on the GMAC1 pins */
779 .pins = pci_3512_pins,
787 .pins = lpc_3512_pins,
789 /* Conflict with SSP and UART modem pins */
795 .pins = lcd_3512_pins,
803 .pins = ssp_3512_pins,
805 /* Conflict with LPC and UART modem pins */
811 .pins = uart_rxtx_3512_pins,
817 .pins = uart_modem_3512_pins,
827 .pins = tvc_3512_pins,
835 .pins = tvc_clk_3512_pins,
848 .pins = nflash_3512_pins,
850 /* Conflict with IDE, parallel and serial flash */
856 .pins = pflash_3512_pins,
858 /* Conflict with IDE, NAND and serial flash */
864 .pins = sflash_3512_pins,
866 /* Conflict with IDE, NAND and parallel flash */
872 .pins = gpio0a_3512_pins,
879 .pins = gpio0b_3512_pins,
886 .pins = gpio0c_3512_pins,
892 .pins = gpio0d_3512_pins,
898 .pins = gpio0e_3512_pins,
900 /* Conflict with LPC, UART modem pins, SSP */
905 .pins = gpio0f_3512_pins,
912 .pins = gpio0g_3512_pins,
919 .pins = gpio0h_3512_pins,
926 .pins = gpio0i_3512_pins,
933 .pins = gpio0j_3512_pins,
941 .pins = gpio0k_3512_pins,
950 .pins = gpio0l_3512_pins,
957 .pins = gpio0m_3512_pins,
964 .pins = gpio1a_3512_pins,
966 /* Conflict with IDE and parallel flash */
972 .pins = gpio1b_3512_pins,
974 /* Conflict with IDE only */
979 .pins = gpio1c_3512_pins,
981 /* Conflict with IDE, parallel and NAND flash */
987 .pins = gpio1d_3512_pins,
994 .pins = gpio2a_3512_pins,
1001 .pins = gpio2b_3512_pins,
1008 .pins = gpio2c_3512_pins,
1228 PINCTRL_PIN(200, "L1 IDE CS0 N"),
1229 PINCTRL_PIN(201, "L2 IDE DA0"),
1232 PINCTRL_PIN(204, "L5 IDE DIOR N"),
1249 PINCTRL_PIN(220, "M1 IDE DA1"),
1250 PINCTRL_PIN(221, "M2 IDE CS1 N"),
1251 PINCTRL_PIN(222, "M3 IDE DA2"),
1252 PINCTRL_PIN(223, "M4 IDE DMACK N"),
1253 PINCTRL_PIN(224, "M5 IDE DD1"),
1270 PINCTRL_PIN(240, "N1 IDE IORDY"),
1271 PINCTRL_PIN(241, "N2 IDE INTRQ"),
1272 PINCTRL_PIN(242, "N3 IDE DIOW N"),
1273 PINCTRL_PIN(243, "N4 IDE DD15"),
1274 PINCTRL_PIN(244, "N5 IDE DMARQ"),
1291 PINCTRL_PIN(260, "P1 IDE DD0"),
1292 PINCTRL_PIN(261, "P2 IDE DD14"),
1293 PINCTRL_PIN(262, "P3 IDE DD2"),
1294 PINCTRL_PIN(263, "P4 IDE DD4"),
1295 PINCTRL_PIN(264, "P5 IDE DD3"),
1312 PINCTRL_PIN(280, "R1 IDE DD13"),
1313 PINCTRL_PIN(281, "R2 IDE DD12"),
1314 PINCTRL_PIN(282, "R3 IDE DD10"),
1315 PINCTRL_PIN(283, "R4 IDE DD6"),
1333 PINCTRL_PIN(300, "T1 IDE DD11"),
1334 PINCTRL_PIN(301, "T2 IDE DD5"),
1335 PINCTRL_PIN(302, "T3 IDE DD8"),
1354 PINCTRL_PIN(320, "U1 IDE DD9"),
1355 PINCTRL_PIN(321, "U2 IDE DD7"),
1396 PINCTRL_PIN(360, "W1 IDE RESET N"),
1483 /* GMII, ethernet pins */
1555 /* NAND flash pins */
1561 /* Parallel (NOR) flash pins, D[0-15], A[16-25], CE0, CE1, RB, WE, OE, ALE */
1569 * The parallel flash can be set up in a 26-bit address bus mode exposing
1570 * A[0-15] (A[15] takes the place of ALE), but it has the
1571 * side effect of stealing pins from GMAC1 and TVC so these blocks cannot be
1578 /* The extra pins */
1583 /* Serial flash pins CE0, CE1, DI, DO, CK */
1586 /* The GPIO0A (0-4) pins overlap with TVC and extended parallel flash */
1589 /* The GPIO0B (5-7) pins overlap with ICE */
1592 /* The GPIO0C (8,11-15) pins overlap with LPC, UART and SSP */
1595 /* The GPIO0D (9,10) pins overlap with UART RX/TX */
1598 /* The GPIO0E (16) pins overlap with LCD */
1601 /* The GPIO0F (17,18) pins overlap with NAND flash CE0, CE1 */
1604 /* The GPIO0G (19,20,26-29) pins overlap with parallel flash */
1607 /* The GPIO0H (21,22) pins overlap with serial flash CE0, CE1 */
1610 /* The GPIO0I (23) pins overlap with all flash */
1613 /* The GPIO0J (24,25) pins overlap with all flash and LCD */
1616 /* The GPIO0K (30,31) pins overlap with NAND flash */
1619 /* The GPIO0L (0) pins overlap with TVC_CLK */
1622 /* The GPIO1A (0-4) pins that overlap with IDE and parallel flash */
1625 /* The GPIO1B (5-10,27) pins overlap with just IDE */
1628 /* The GPIO1C (11-26) pins overlap with IDE, parallel flash and NAND flash */
1634 /* The GPIO1D (28-31) pins overlap with TVC */
1637 /* The GPIO2A (0-3) pins overlap with GMII GMAC1 and extended parallel flash */
1640 /* The GPIO2B (4-7) pins overlap with GMII GMAC1, extended parallel flash and LCD */
1643 /* The GPIO2C (8-31) pins overlap with PCI */
1653 .pins = gnd_3516_pins,
1658 .pins = dram_3516_pins,
1664 .pins = rtc_3516_pins,
1669 .pins = power_3516_pins,
1674 .pins = cir_3516_pins,
1679 .pins = system_3516_pins,
1684 .pins = vcontrol_3516_pins,
1689 .pins = ice_3516_pins,
1695 .pins = ide_3516_pins,
1704 .pins = sata_3516_pins,
1709 .pins = usb_3516_pins,
1714 .pins = gmii_gmac0_3516_pins,
1721 .pins = gmii_gmac1_3516_pins,
1723 /* Bring out RGMII on the GMAC1 pins */
1730 .pins = pci_3516_pins,
1738 .pins = lpc_3516_pins,
1746 .pins = lcd_3516_pins,
1753 .pins = ssp_3516_pins,
1761 .pins = uart_rxtx_3516_pins,
1767 .pins = uart_modem_3516_pins,
1777 .pins = tvc_3516_pins,
1785 .pins = tvc_clk_3516_pins,
1798 .pins = nflash_3516_pins,
1800 /* Conflict with IDE, parallel and serial flash */
1806 .pins = pflash_3516_pins,
1808 /* Conflict with IDE, NAND and serial flash */
1814 .pins = sflash_3516_pins,
1816 /* Conflict with IDE, NAND and parallel flash */
1822 .pins = gpio0a_3516_pins,
1829 .pins = gpio0b_3516_pins,
1835 .pins = gpio0c_3516_pins,
1842 .pins = gpio0d_3516_pins,
1848 .pins = gpio0e_3516_pins,
1855 .pins = gpio0f_3516_pins,
1862 .pins = gpio0g_3516_pins,
1869 .pins = gpio0h_3516_pins,
1876 .pins = gpio0i_3516_pins,
1884 .pins = gpio0j_3516_pins,
1893 .pins = gpio0k_3516_pins,
1900 .pins = gpio0l_3516_pins,
1907 .pins = gpio1a_3516_pins,
1909 /* Conflict with IDE and parallel flash */
1915 .pins = gpio1b_3516_pins,
1917 /* Conflict with IDE only */
1922 .pins = gpio1c_3516_pins,
1924 /* Conflict with IDE, parallel and NAND flash */
1930 .pins = gpio1d_3516_pins,
1937 .pins = gpio2a_3516_pins,
1944 .pins = gpio2b_3516_pins,
1951 .pins = gpio2c_3516_pins,
1962 if (pmx->is_3512) in gemini_get_groups_count()
1964 if (pmx->is_3516) in gemini_get_groups_count()
1974 if (pmx->is_3512) in gemini_get_group_name()
1976 if (pmx->is_3516) in gemini_get_group_name()
1983 const unsigned int **pins, in gemini_get_group_pins() argument
1989 if (pmx->flash_pin && in gemini_get_group_pins()
1990 pmx->is_3512 && in gemini_get_group_pins()
1992 *pins = pflash_3512_pins_extended; in gemini_get_group_pins()
1996 if (pmx->flash_pin && in gemini_get_group_pins()
1997 pmx->is_3516 && in gemini_get_group_pins()
1999 *pins = pflash_3516_pins_extended; in gemini_get_group_pins()
2003 if (pmx->is_3512) { in gemini_get_group_pins()
2004 *pins = gemini_3512_pin_groups[selector].pins; in gemini_get_group_pins()
2007 if (pmx->is_3516) { in gemini_get_group_pins()
2008 *pins = gemini_3516_pin_groups[selector].pins; in gemini_get_group_pins()
2030 * struct gemini_pmx_func - describes Gemini pinmux functions
2107 .name = "ide",
2203 if (pmx->is_3512) in gemini_pmx_set_mux()
2205 else if (pmx->is_3516) in gemini_pmx_set_mux()
2208 dev_err(pmx->dev, "invalid SoC type\n"); in gemini_pmx_set_mux()
2209 return -ENODEV; in gemini_pmx_set_mux()
2212 dev_dbg(pmx->dev, in gemini_pmx_set_mux()
2214 func->name, grp->name); in gemini_pmx_set_mux()
2216 regmap_read(pmx->map, GLOBAL_MISC_CTRL, &before); in gemini_pmx_set_mux()
2217 regmap_update_bits(pmx->map, GLOBAL_MISC_CTRL, in gemini_pmx_set_mux()
2218 grp->mask | grp->value, in gemini_pmx_set_mux()
2219 grp->value); in gemini_pmx_set_mux()
2220 regmap_read(pmx->map, GLOBAL_MISC_CTRL, &after); in gemini_pmx_set_mux()
2225 expected = before &= ~grp->mask; in gemini_pmx_set_mux()
2226 expected |= grp->value; in gemini_pmx_set_mux()
2230 tmp = grp->mask; in gemini_pmx_set_mux()
2236 dev_err(pmx->dev, in gemini_pmx_set_mux()
2241 dev_err(pmx->dev, in gemini_pmx_set_mux()
2245 dev_dbg(pmx->dev, in gemini_pmx_set_mux()
2252 tmp = grp->value; in gemini_pmx_set_mux()
2258 dev_err(pmx->dev, in gemini_pmx_set_mux()
2263 dev_err(pmx->dev, in gemini_pmx_set_mux()
2267 dev_dbg(pmx->dev, in gemini_pmx_set_mux()
2371 for (i = 0; i < pmx->nconfs; i++) { in gemini_get_pin_conf()
2372 retconf = &pmx->confs[i]; in gemini_get_pin_conf()
2373 if (retconf->pin == pin) in gemini_get_pin_conf()
2391 return -ENOTSUPP; in gemini_pinconf_get()
2392 regmap_read(pmx->map, conf->reg, &val); in gemini_pinconf_get()
2393 val &= conf->mask; in gemini_pinconf_get()
2394 val >>= (ffs(conf->mask) - 1); in gemini_pinconf_get()
2398 return -ENOTSUPP; in gemini_pinconf_get()
2421 return -EINVAL; in gemini_pinconf_set()
2424 dev_err(pmx->dev, in gemini_pinconf_set()
2426 return -ENOTSUPP; in gemini_pinconf_set()
2428 arg <<= (ffs(conf->mask) - 1); in gemini_pinconf_set()
2429 dev_dbg(pmx->dev, in gemini_pinconf_set()
2431 pin, conf->mask, arg); in gemini_pinconf_set()
2432 regmap_update_bits(pmx->map, conf->reg, conf->mask, arg); in gemini_pinconf_set()
2435 dev_err(pmx->dev, "Invalid config param %04x\n", param); in gemini_pinconf_set()
2436 return -ENOTSUPP; in gemini_pinconf_set()
2455 if (pmx->is_3512) in gemini_pinconf_group_set()
2457 if (pmx->is_3516) in gemini_pinconf_group_set()
2461 if (!grp->driving_mask) { in gemini_pinconf_group_set()
2462 dev_err(pmx->dev, "pin config group \"%s\" does " in gemini_pinconf_group_set()
2464 grp->name); in gemini_pinconf_group_set()
2465 return -EINVAL; in gemini_pinconf_group_set()
2488 dev_err(pmx->dev, in gemini_pinconf_group_set()
2491 return -ENOTSUPP; in gemini_pinconf_group_set()
2493 val <<= (ffs(grp->driving_mask) - 1); in gemini_pinconf_group_set()
2494 regmap_update_bits(pmx->map, GLOBAL_IODRIVE, in gemini_pinconf_group_set()
2495 grp->driving_mask, in gemini_pinconf_group_set()
2497 dev_dbg(pmx->dev, in gemini_pinconf_group_set()
2499 grp->name, arg, grp->driving_mask, val); in gemini_pinconf_group_set()
2502 dev_err(pmx->dev, "invalid config param %04x\n", param); in gemini_pinconf_group_set()
2503 return -ENOTSUPP; in gemini_pinconf_group_set()
2529 struct device *dev = &pdev->dev; in gemini_pmx_probe()
2537 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); in gemini_pmx_probe()
2539 return -ENOMEM; in gemini_pmx_probe()
2541 pmx->dev = &pdev->dev; in gemini_pmx_probe()
2542 parent = dev->parent; in gemini_pmx_probe()
2545 return -ENODEV; in gemini_pmx_probe()
2547 map = syscon_node_to_regmap(parent->of_node); in gemini_pmx_probe()
2552 pmx->map = map; in gemini_pmx_probe()
2563 pmx->is_3512 = true; in gemini_pmx_probe()
2564 pmx->confs = gemini_confs_3512; in gemini_pmx_probe()
2565 pmx->nconfs = ARRAY_SIZE(gemini_confs_3512); in gemini_pmx_probe()
2566 gemini_pmx_desc.pins = gemini_3512_pins; in gemini_pmx_probe()
2570 pmx->is_3516 = true; in gemini_pmx_probe()
2571 pmx->confs = gemini_confs_3516; in gemini_pmx_probe()
2572 pmx->nconfs = ARRAY_SIZE(gemini_confs_3516); in gemini_pmx_probe()
2573 gemini_pmx_desc.pins = gemini_3516_pins; in gemini_pmx_probe()
2578 return -ENODEV; in gemini_pmx_probe()
2596 pmx->flash_pin = !!(val & GLOBAL_STATUS_FLPIN); in gemini_pmx_probe()
2597 dev_info(dev, "flash pin is %s\n", pmx->flash_pin ? "set" : "not set"); in gemini_pmx_probe()
2599 pmx->pctl = devm_pinctrl_register(dev, &gemini_pmx_desc, pmx); in gemini_pmx_probe()
2600 if (IS_ERR(pmx->pctl)) { in gemini_pmx_probe()
2602 return PTR_ERR(pmx->pctl); in gemini_pmx_probe()
2605 dev_info(dev, "initialized Gemini pin control driver\n"); in gemini_pmx_probe()
2611 { .compatible = "cortina,gemini-pinctrl" },