Home
last modified time | relevance | path

Searched +full:gcc +full:- +full:msm8909 (Results 1 – 8 of 8) sorted by relevance

/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,gcc-msm8909.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-msm8909.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on MSM8909, MSM8917 and QM215
10 - Stephan Gerhold <stephan@gerhold.net>
14 domains on MSM8909, MSM8917 or QM215.
17 include/dt-bindings/clock/qcom,gcc-msm8909.h
18 include/dt-bindings/clock/qcom,gcc-msm8917.h
23 - qcom,gcc-msm8909
[all …]
/linux/drivers/clk/qcom/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_COMMON_CLK_QCOM) += clk-qcom.o
4 clk-qcom-y += common.o
5 clk-qcom-y += clk-regmap.o
6 clk-qcom-y += clk-alpha-pll.o
7 clk-qcom-y += clk-pll.o
8 clk-qcom-y += clk-rcg.o
9 clk-qcom-y += clk-rcg2.o
10 clk-qcom-y += clk-branch.o
11 clk-qcom-y += clk-regmap-divider.o
[all …]
H A Dgcc-msm8909.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Based on gcc-msm8916.c:
7 * adapted with data from clock-gcc-8909.c in Qualcomm's msm-3.18 release:
8 * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
12 #include <linux/clk-provider.h>
19 #include <linux/reset-controller.h>
21 #include <dt-bindings/clock/qcom,gcc-msm8909.h>
23 #include "clk-alpha-pll.h"
24 #include "clk-branch.h"
25 #include "clk-pll.h"
[all …]
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
276 tristate "MSM8909 Global Clock Controller"
280 Support for the global clock controller on msm8909 devices.
1251 tristate "High-Frequency PLL (HFPLL) Clock Controller"
1253 Support for the high-frequency PLLs present on Qualcomm devices.
1260 Support for the Krait ACC and GCC clock controllers. Say Y
/linux/Documentation/devicetree/bindings/remoteproc/
H A Dqcom,msm8916-mss-pil.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,msm8916-mss-pil.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stephan Gerhold <stephan@gerhold.net>
19 - enum:
20 - qcom,msm8909-mss-pil
21 - qcom,msm8916-mss-pil
22 - qcom,msm8953-mss-pil
23 - qcom,msm8974-mss-pil
[all …]
/linux/arch/arm/mach-qcom/
H A Dplatsmp.c1 // SPDX-License-Identifier: GPL-2.0-only
59 node = of_find_compatible_node(NULL, NULL, "qcom,gcc-msm8660"); in scss_release_secondary()
62 return -ENXIO; in scss_release_secondary()
68 return -ENOMEM; in scss_release_secondary()
88 return -ENODEV; in cortex_a7_release_secondary()
92 ret = -ENODEV; in cortex_a7_release_secondary()
98 ret = -ENOMEM; in cortex_a7_release_secondary()
144 return -ENODEV; in kpssv1_release_secondary()
148 ret = -ENODEV; in kpssv1_release_secondary()
154 ret = -ENODEV; in kpssv1_release_secondary()
[all …]
/linux/Documentation/devicetree/bindings/arm/
H A Dcpus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
59 On 32-bit ARM v7 or later systems this property is
68 On ARM v8 64-bit systems this property is required
71 * If cpus node's #address-cells property is set to 2
79 * If cpus node's #address-cells property is set to 1
[all …]
/linux/drivers/thermal/qcom/
H A Dtsens.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/nvmem-consumer.h>
26 * struct tsens_irq_data - IRQ status and temperature violations
81 if (priv->num_sensors > MAX_SENSORS) in tsens_read_calibration()
82 return -EINVAL; in tsens_read_calibration()
88 ret = nvmem_cell_read_variable_le_u32(priv->dev, name, &mode); in tsens_read_calibration()
89 if (ret == -ENOENT) in tsens_read_calibration()
90 dev_warn(priv->dev, "Please migrate to separate nvmem cells for calibration data\n"); in tsens_read_calibration()
94 dev_dbg(priv->dev, "calibration mode is %d\n", mode); in tsens_read_calibration()
100 ret = nvmem_cell_read_variable_le_u32(priv->dev, name, &base1); in tsens_read_calibration()
[all …]