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Searched +full:gcc +full:- +full:mdm9615 (Results 1 – 7 of 7) sorted by relevance

/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,gcc-mdm9615.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-mdm9615.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <quic_tdas@quicinc.com>
18 include/dt-bindings/clock/qcom,gcc-mdm9615.h
21 - $ref: qcom,gcc.yaml#
26 - qcom,gcc-mdm9615
30 - description: CXO clock
[all …]
H A Dqcom,kpss-gcc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,kpss-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Krait Processor Sub-system (KPSS) Global Clock Controller (GCC)
10 - Christian Marangi <ansuelsmth@gmail.com>
13 Krait Processor Sub-system (KPSS) Global Clock Controller (GCC). Used
15 to the kpss-gcc registers.
20 - enum:
21 - qcom,kpss-gcc-ipq8064
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Dqcom,usb-hsic-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,usb-hsic-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Vinod Koul <vkoul@kernel.org>
16 - enum:
17 - qcom,usb-hsic-phy-mdm9615
18 - qcom,usb-hsic-phy-msm8974
19 - const: qcom,usb-hsic-phy
[all …]
/linux/arch/arm/boot/dts/qcom/
H A Dqcom-mdm9615-wp8548.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
9 #include "qcom-mdm9615.dtsi"
14 compatible = "swir,wp8548", "qcom,mdm9615";
23 pinctrl-0 = <&reset_out_pins>;
24 pinctrl-names = "default";
26 gsbi3_pins: gsbi3-state {
27 gsbi3-pins {
30 drive-strength = <8>;
31 bias-disable;
35 gsbi4_pins: gsbi4-state {
[all …]
/linux/drivers/clk/qcom/
H A Dgcc-mdm9615.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
14 #include <linux/clk-provider.h>
16 #include <linux/reset-controller.h>
18 #include <dt-bindings/clock/qcom,gcc-mdm9615.h>
19 #include <dt-bindings/reset/qcom,gcc-mdm9615.h>
22 #include "clk-regmap.h"
23 #include "clk-pll.h"
24 #include "clk-rcg.h"
25 #include "clk-branch.h"
[all …]
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_COMMON_CLK_QCOM) += clk-qcom.o
4 clk-qcom-y += common.o
5 clk-qcom-y += clk-regmap.o
6 clk-qcom-y += clk-alpha-pll.o
7 clk-qcom-y += clk-pll.o
8 clk-qcom-y += clk-rcg.o
9 clk-qcom-y += clk-rcg2.o
10 clk-qcom-y += clk-branch.o
11 clk-qcom-y += clk-regmap-divider.o
[all …]
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
242 CMN PLL consumes the AHB/SYS clocks from GCC and supplies
243 the output clocks to the networking hardware and GCC blocks.
405 tristate "MDM9615 Global Clock Controller"
408 Support for the global clock controller on mdm9615 devices.
1411 Say Y if you want to toggle LPASS-adjacent resets within
1529 tristate "High-Frequency PLL (HFPLL) Clock Controller"
1531 Support for the high-frequency PLLs present on Qualcomm devices.
1538 Support for the Krait ACC and GCC clock controllers. Say Y