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Searched +full:gcc +full:- +full:ipq806x (Results 1 – 16 of 16) sorted by relevance

/linux/arch/arm/boot/dts/qcom/
H A Dqcom-ipq8064.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mfd/qcom-rpm.h>
6 #include <dt-bindings/clock/qcom,rpmcc.h>
7 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
8 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
11 #include <dt-bindings/soc/qcom,gsbi.h>
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/linux/Documentation/devicetree/bindings/phy/
H A Dqcom,ipq806x-usb-phy-hs.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,ipq806x-usb-phy-hs.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm ipq806x usb DWC3 HS PHY CONTROLLER
10 - Ansuel Smith <ansuelsmth@gmail.com>
13 DWC3 PHY nodes are defined to describe on-chip Synopsis Physical layer
14 controllers used in ipq806x. Each DWC3 PHY controller should have its
19 const: qcom,ipq806x-usb-phy-hs
21 "#phy-cells":
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H A Dqcom,ipq806x-usb-phy-ss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,ipq806x-usb-phy-ss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm ipq806x usb DWC3 SS PHY CONTROLLER
10 - Ansuel Smith <ansuelsmth@gmail.com>
13 DWC3 PHY nodes are defined to describe on-chip Synopsis Physical layer
14 controllers used in ipq806x. Each DWC3 PHY controller should have its
19 const: qcom,ipq806x-usb-phy-ss
21 "#phy-cells":
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H A Dqcom,sata-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,sata-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Konrad Dybcio <konrad.dybcio@linaro.org>
14 The Qualcomm SATA PHY describes on-chip SATA Physical layer controllers.
19 - qcom,ipq806x-sata-phy
20 - qcom,apq8064-sata-phy
28 clock-names:
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/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,gcc-ipq8064.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-ipq8064.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ansuel Smith <ansuelsmth@gmail.com>
17 include/dt-bindings/clock/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
18 include/dt-bindings/reset/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
21 - $ref: qcom,gcc.yaml#
26 - const: qcom,gcc-ipq8064
27 - const: syscon
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H A Dqcom,kpss-gcc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,kpss-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Krait Processor Sub-system (KPSS) Global Clock Controller (GCC)
10 - Christian Marangi <ansuelsmth@gmail.com>
13 Krait Processor Sub-system (KPSS) Global Clock Controller (GCC). Used
15 to the kpss-gcc registers.
20 - enum:
21 - qcom,kpss-gcc-ipq8064
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H A Dqcom,kpss-acc-v1.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,kpss-acc-v1.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Krait Processor Sub-system (KPSS) Application Clock Controller (ACC) v1
10 - Christian Marangi <ansuelsmth@gmail.com>
17 clock-controller for enabling the cpu and handling the aux clocks.
21 const: qcom,kpss-acc-v1
25 - description: Base address and size of the register region
26 - description: Optional base address and size of the alias register region
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/linux/Documentation/devicetree/bindings/mtd/
H A Dqcom,nandc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
15 - qcom,ipq806x-nand
16 - qcom,ipq4019-nand
17 - qcom,ipq6018-nand
18 - qcom,ipq8074-nand
19 - qcom,sdx55-nand
26 - description: Core Clock
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/linux/Documentation/devicetree/bindings/net/
H A Dipq806x-dwmac.txt1 * IPQ806x DWMAC Ethernet controller
8 - compatible: should be "qcom,ipq806x-gmac" along with "snps,dwmac"
12 - qcom,nss-common: should contain a phandle to a syscon device mapping the
13 nss-common registers.
15 - qcom,qsgmii-csr: should contain a phandle to a syscon device mapping the
16 qsgmii-csr registers.
22 compatible = "qcom,ipq806x-gmac";
25 interrupt-names = "macirq";
27 qcom,nss-common = <&nss_common>;
28 qcom,qsgmii-csr = <&qsgmii_csr>;
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H A Dqcom,ipq8064-mdio.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/qcom,ipq8064-mdio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm ipq806x MDIO bus controller
10 - Ansuel Smith <ansuelsmth@gmail.com>
13 The ipq806x soc have a MDIO dedicated controller that is
17 - $ref: mdio.yaml#
21 const: qcom,ipq8064-mdio
30 - compatible
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/linux/Documentation/devicetree/bindings/dma/
H A Dqcom,adm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christian Marangi <ansuelsmth@gmail.com>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
27 "#dma-cells":
32 - description: phandle to the core clock
33 - description: phandle to the iface clock
35 clock-names:
37 - const: core
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/linux/Documentation/devicetree/bindings/arm/
H A Dqcom-soc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/qcom-soc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
15 qcom,SoC-IP
18 qcom,sdm845-llcc-bwmon
26 pattern: "^qcom,.*(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1e)[0-9]+.*$"
28 - compatible
34 - pattern: "^qcom,(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1e)[0-9]+(pro)?-.*$"
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/linux/drivers/clk/qcom/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_COMMON_CLK_QCOM) += clk-qcom.o
4 clk-qcom-y += common.o
5 clk-qcom-y += clk-regmap.o
6 clk-qcom-y += clk-alpha-pll.o
7 clk-qcom-y += clk-pll.o
8 clk-qcom-y += clk-rcg.o
9 clk-qcom-y += clk-rcg2.o
10 clk-qcom-y += clk-branch.o
11 clk-qcom-y += clk-regmap-divider.o
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
225 tristate "IPQ806x Global Clock Controller"
228 Support for the global clock controller on ipq806x devices.
233 tristate "IPQ806x LPASS Clock Controller"
237 Support for the LPASS clock controller on ipq806x devices.
1251 tristate "High-Frequency PLL (HFPLL) Clock Controller"
1253 Support for the high-frequency PLLs present on Qualcomm devices.
1260 Support for the Krait ACC and GCC clock controllers. Say Y
H A Dgcc-ipq806x.c1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <linux/clk-provider.h>
15 #include <linux/reset-controller.h>
17 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
18 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
21 #include "clk-regmap.h"
22 #include "clk-pll.h"
23 #include "clk-rcg.h"
24 #include "clk-branch.h"
25 #include "clk-hfpll.h"
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/linux/Documentation/devicetree/bindings/firmware/
H A Dqcom,scm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
16 - Bjorn Andersson <bjorn.andersson@linaro.org>
17 - Robert Marko <robimarko@gmail.com>
18 - Guru Das Srinagesh <quic_gurus@quicinc.com>
23 - enum:
24 - qcom,scm-apq8064
25 - qcom,scm-apq8084
26 - qcom,scm-ipq4019
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