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Searched +full:gcc +full:- +full:ipq5424 (Results 1 – 14 of 14) sorted by relevance

/linux/arch/arm64/boot/dts/qcom/
H A Dipq5424.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * IPQ5424 device tree source
5 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/qcom,apss-ipq.h>
11 #include <dt-bindings/clock/qcom,ipq5424-cmn-pll.h>
12 #include <dt-bindings/clock/qcom,ipq5424-gcc.h>
13 #include <dt-bindings/reset/qcom,ipq5424-gcc.h>
14 #include <dt-bindings/interconnect/qcom,ipq5424.h>
15 #include <dt-bindings/gpio/gpio.h>
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/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,ipq5332-gcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,ipq5332-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on IPQ5332 and IPQ5424
10 - Bjorn Andersson <andersson@kernel.org>
14 domains on IPQ5332 and IPQ5424.
17 include/dt-bindings/clock/qcom,gcc-ipq5332.h
18 include/dt-bindings/clock/qcom,gcc-ipq5424.h
23 - qcom,ipq5332-gcc
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H A Dqcom,ipq9574-nsscc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,ipq9574-nsscc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ9574 and IPQ5424
10 - Bjorn Andersson <andersson@kernel.org>
11 - Anusha Rao <quic_anusha@quicinc.com>
15 resets on IPQ9574 and IPQ5424
18 include/dt-bindings/clock/qcom,ipq5424-nsscc.h
19 include/dt-bindings/clock/qcom,ipq9574-nsscc.h
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H A Dqcom,ipq5424-apss-clk.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,ipq5424-apss-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm APSS IPQ5424 Clock Controller
10 - Varadarajan Narayanan <quic_varada@quicinc.com>
13 The CPU core in ipq5424 is clocked by a huayra PLL with RCG support.
14 The RCG and PLL have a separate register space from the GCC.
19 - qcom,ipq5424-apss-clk
26 - description: Reference to the XO clock.
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/linux/drivers/clk/qcom/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_COMMON_CLK_QCOM) += clk-qcom.o
4 clk-qcom-y += common.o
5 clk-qcom-y += clk-regmap.o
6 clk-qcom-y += clk-alpha-pll.o
7 clk-qcom-y += clk-pll.o
8 clk-qcom-y += clk-rcg.o
9 clk-qcom-y += clk-rcg2.o
10 clk-qcom-y += clk-branch.o
11 clk-qcom-y += clk-regmap-divider.o
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H A Dipq-cmn-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
7 * CMN PLL block expects the reference clock from on-board Wi-Fi block,
9 * blocks and to GCC. The networking related blocks include PPE (packet
16 * are supplied to GCC (24 MHZ as XO and 32 KHZ as sleep clock), and to PCS
19 * On the IPQ5424 SoC, there is an output clock from CMN PLL to PPE at 375 MHZ,
21 * clocks from CMN PLL on IPQ5424 are the same as IPQ9574.
23 * +---------+
24 * | GCC |
25 * +--+---+--+
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
218 tristate "IPQ5424 APSS Clock Controller"
222 Support for APSS Clock controller on Qualcomm IPQ5424 platform.
242 CMN PLL consumes the AHB/SYS clocks from GCC and supplies
243 the output clocks to the networking hardware and GCC blocks.
271 tristate "IPQ5424 Global Clock Controller"
274 Support for the global clock controller on ipq5424 devices.
321 tristate "IPQ5424 NSS Clock Controller"
325 Support for NSS clock controller on ipq5424 devices.
326 NSSCC receives the clock sources from GCC, CMN PLL and UNIPHY (PCS).
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H A Dgcc-ipq5424.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
8 #include <linux/interconnect-provider.h>
15 #include <dt-bindings/clock/qcom,ipq5424-gcc.h>
16 #include <dt-bindings/interconnect/qcom,ipq5424.h>
17 #include <dt-bindings/reset/qcom,ipq5424-gcc.h>
19 #include "clk-alpha-pll.h"
20 #include "clk-branch.h"
21 #include "clk-rcg.h"
22 #include "clk-regmap.h"
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/linux/Documentation/devicetree/bindings/firmware/
H A Dqcom,scm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
16 - Bjorn Andersson <bjorn.andersson@linaro.org>
17 - Robert Marko <robimarko@gmail.com>
18 - Guru Das Srinagesh <quic_gurus@quicinc.com>
23 - enum:
24 - qcom,scm-apq8064
25 - qcom,scm-apq8084
26 - qcom,scm-glymur
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/linux/Documentation/devicetree/bindings/nvmem/
H A Dqcom,qfprom.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
13 - $ref: nvmem.yaml#
14 - $ref: nvmem-deprecated-cells.yaml#
19 - enum:
20 - qcom,apq8064-qfprom
21 - qcom,apq8084-qfprom
22 - qcom,ipq5018-qfprom
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/linux/Documentation/devicetree/bindings/usb/
H A Dqcom,snps-dwc3.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/qcom,snps-dwc3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wesley Cheng <quic_wcheng@quicinc.com>
19 const: qcom,snps-dwc3
21 - compatible
26 - enum:
27 - qcom,glymur-dwc3
28 - qcom,glymur-dwc3-mp
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H A Dqcom,dwc3.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wesley Cheng <quic_wcheng@quicinc.com>
12 # Use the combined qcom,snps-dwc3 instead
21 - compatible
26 - enum:
27 - qcom,ipq4019-dwc3
28 - qcom,ipq5018-dwc3
29 - qcom,ipq5332-dwc3
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/linux/drivers/thermal/qcom/
H A Dtsens.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/nvmem-consumer.h>
26 * struct tsens_irq_data - IRQ status and temperature violations
81 if (priv->num_sensors > MAX_SENSORS) in tsens_read_calibration()
82 return -EINVAL; in tsens_read_calibration()
88 ret = nvmem_cell_read_variable_le_u32(priv->dev, name, &mode); in tsens_read_calibration()
89 if (ret == -ENOENT) in tsens_read_calibration()
90 dev_warn(priv->dev, "Please migrate to separate nvmem cells for calibration data\n"); in tsens_read_calibration()
94 dev_dbg(priv->dev, "calibration mode is %d\n", mode); in tsens_read_calibration()
100 ret = nvmem_cell_read_variable_le_u32(priv->dev, name, &base1); in tsens_read_calibration()
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/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-usb.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
22 #include "phy-qcom-qmp-common.h"
24 #include "phy-qcom-qmp.h"
25 #include "phy-qcom-qmp-pcs-misc-v3.h"
26 #include "phy-qcom-qmp-pcs-misc-v4.h"
27 #include "phy-qcom-qmp-pcs-usb-v4.h"
28 #include "phy-qcom-qmp-pcs-usb-v5.h"
29 #include "phy-qcom-qmp-pcs-usb-v6.h"
30 #include "phy-qcom-qmp-pcs-usb-v7.h"
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