Home
last modified time | relevance | path

Searched +full:gcc +full:- +full:apq8084 (Results 1 – 9 of 9) sorted by relevance

/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,gcc-apq8084.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-apq8084.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on APQ8084
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <quic_tdas@quicinc.com>
15 domains on APQ8084.
18 include/dt-bindings/clock/qcom,gcc-apq8084.h
19 include/dt-bindings/reset/qcom,gcc-apq8084.h
[all …]
/linux/arch/arm/boot/dts/qcom/
H A Dqcom-apq8084.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-apq8084.h>
6 #include <dt-bindings/gpio/gpio.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
12 compatible = "qcom,apq8084";
13 interrupt-parent = <&intc>;
15 reserved-memory {
[all …]
/linux/Documentation/devicetree/bindings/pci/
H A Dqcom,pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
20 - enum:
21 - qcom,pcie-apq8064
22 - qcom,pcie-apq8084
23 - qcom,pcie-ipq4019
24 - qcom,pcie-ipq5018
[all …]
/linux/Documentation/devicetree/bindings/display/msm/
H A Dqcom,mdp5.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 MDP5 display controller found in SoCs like MSM8974, APQ8084, MSM8916, MSM8994
14 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
15 - Rob Clark <robdclark@gmail.com>
20 - const: qcom,mdp5
22 - items:
23 - enum:
24 - qcom,apq8084-mdp5
[all …]
/linux/drivers/clk/qcom/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_COMMON_CLK_QCOM) += clk-qcom.o
4 clk-qcom-y += common.o
5 clk-qcom-y += clk-regmap.o
6 clk-qcom-y += clk-alpha-pll.o
7 clk-qcom-y += clk-pll.o
8 clk-qcom-y += clk-rcg.o
9 clk-qcom-y += clk-rcg2.o
10 clk-qcom-y += clk-branch.o
11 clk-qcom-y += clk-regmap-divider.o
[all …]
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
179 platforms such as apq8016, apq8084, msm8974 etc.
191 tristate "APQ8084 Global Clock Controller"
195 Support for the global clock controller on apq8084 devices.
200 tristate "APQ8084 Multimedia Clock Controller"
205 Support for the multimedia clock controller on apq8084 devices.
242 CMN PLL consumes the AHB/SYS clocks from GCC and supplies
243 the output clocks to the networking hardware and GCC blocks.
1411 Say Y if you want to toggle LPASS-adjacent resets within
1529 tristate "High-Frequency PLL (HFPLL) Clock Controller"
[all …]
H A Dgcc-apq8084.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/clk-provider.h>
14 #include <linux/reset-controller.h>
16 #include <dt-bindings/clock/qcom,gcc-apq8084.h>
17 #include <dt-bindings/reset/qcom,gcc-apq8084.h>
20 #include "clk-regmap.h"
21 #include "clk-pll.h"
22 #include "clk-rcg.h"
23 #include "clk-branch.h"
3618 { .compatible = "qcom,gcc-apq8084" },
[all …]
/linux/Documentation/devicetree/bindings/dma/
H A Dqcom,bam-dma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/qcom,bam-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andy Gross <agross@kernel.org>
11 - Bjorn Andersson <andersson@kernel.org>
14 - $ref: dma-controller.yaml#
19 - enum:
21 - qcom,bam-v1.3.0
22 # MSM8974, APQ8074 and APQ8084
[all …]
/linux/Documentation/devicetree/bindings/nvmem/
H A Dqcom,qfprom.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
13 - $ref: nvmem.yaml#
14 - $ref: nvmem-deprecated-cells.yaml#
19 - enum:
20 - qcom,apq8064-qfprom
21 - qcom,apq8084-qfprom
22 - qcom,ipq5018-qfprom
[all …]