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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dqcom,gcc-apq8064.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-apq8064.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on APQ8064/MSM8960
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <quic_tdas@quicinc.com>
15 domains on APQ8064.
18 include/dt-bindings/clock/qcom,gcc-msm8960.h
19 include/dt-bindings/reset/qcom,gcc-msm8960.h
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H A Dqcom,kpss-gcc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,kpss-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Krait Processor Sub-system (KPSS) Global Clock Controller (GCC)
10 - Christian Marangi <ansuelsmth@gmail.com>
13 Krait Processor Sub-system (KPSS) Global Clock Controller (GCC). Used
15 to the kpss-gcc registers.
20 - enum:
21 - qcom,kpss-gcc-ipq8064
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/freebsd/sys/contrib/device-tree/src/arm/qcom/
H A Dqcom-apq8064.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
5 #include <dt-bindings/clock/qcom,lcc-msm8960.h>
6 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/soc/qcom,gsbi.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
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/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dqcom,pcie.txt3 - compatible:
7 - "qcom,pcie-ipq8064" for ipq8064
8 - "qcom,pcie-ipq8064-v2" for ipq8064 rev 2 or ipq8065
9 - "qcom,pcie-apq8064" for apq8064
10 - "qcom,pcie-apq8084" for apq8084
11 - "qcom,pcie-msm8996" for msm8996 or apq8096
12 - "qcom,pcie-ipq4019" for ipq4019
13 - "qcom,pcie-ipq8074" for ipq8074
14 - "qcom,pcie-qcs404" for qcs404
15 - "qcom,pcie-sc8180x" for sc8180x
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H A Dqcom,pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
20 - enum:
21 - qcom,pcie-apq8064
22 - qcom,pcie-apq8084
23 - qcom,pcie-ipq4019
24 - qcom,pcie-ipq6018
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/freebsd/sys/contrib/device-tree/Bindings/firmware/
H A Dqcom,scm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
16 - Bjorn Andersson <bjorn.andersson@linaro.org>
17 - Robert Marko <robimarko@gmail.com>
18 - Guru Das Srinagesh <quic_gurus@quicinc.com>
23 - enum:
24 - qcom,scm-apq8064
25 - qcom,scm-apq8084
26 - qcom,scm-ipq4019
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H A Dqcom,scm.txt9 - compatible: must contain one of the following:
10 * "qcom,scm-apq8064"
11 * "qcom,scm-apq8084"
12 * "qcom,scm-ipq4019"
13 * "qcom,scm-ipq806x"
14 * "qcom,scm-ipq8074"
15 * "qcom,scm-mdm9607"
16 * "qcom,scm-msm8226"
17 * "qcom,scm-msm8660"
18 * "qcom,scm-msm8916"
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/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dqcom-apq8064-sata-phy.txt1 Qualcomm APQ8064 SATA PHY Controller
2 ------------------------------------
4 SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
8 - compatible: compatible list, contains "qcom,apq8064-sata-phy".
9 - reg: offset and length of the SATA PHY register set;
10 - #phy-cells: must be zero
11 - clocks: a list of phandles and clock-specifier pairs, one for each entry in
12 clock-names.
13 - clock-names: must be "cfg" for phy config clock.
16 sata_phy: sata-phy@1b400000 {
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H A Dqcom,usb-hs-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,usb-hs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
17 - qcom,usb-hs-phy-apq8064
18 - qcom,usb-hs-phy-msm8660
19 - qcom,usb-hs-phy-msm8960
25 reset-names:
34 reset-names:
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H A Dqcom,sata-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,sata-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Konrad Dybcio <konrad.dybcio@linaro.org>
14 The Qualcomm SATA PHY describes on-chip SATA Physical layer controllers.
19 - qcom,ipq806x-sata-phy
20 - qcom,apq8064-sata-phy
28 clock-names:
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H A Dqcom,usb-hs-phy.txt5 - compatible:
8 Definition: Should contain "qcom,usb-hs-phy" and more specifically one of the
11 "qcom,usb-hs-phy-apq8064"
12 "qcom,usb-hs-phy-msm8916"
13 "qcom,usb-hs-phy-msm8974"
15 - #phy-cells:
20 - clocks:
22 Value type: <prop-encoded-array>
26 - clock-names:
32 - resets:
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/freebsd/sys/contrib/device-tree/Bindings/soc/qcom/
H A Dqcom,gsbi.txt4 representing a serial sub-node device that is mux'd as part of the GSBI
9 - compatible: Should contain "qcom,gsbi-v1.0.0"
10 - cell-index: Should contain the GSBI index
11 - reg: Address range for GSBI registers
12 - clocks: required clock
13 - clock-names: must contain "iface" entry
14 - qcom,mode : indicates MUX value for configuration of the serial interface.
15 Please reference dt-bindings/soc/qcom,gsbi.h for valid mux values.
18 - qcom,crci : indicates CRCI MUX value for QUP CRCI ports. Please reference
19 dt-bindings/soc/qcom,gsbi.h for valid CRCI mux values.
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/freebsd/sys/contrib/device-tree/Bindings/arm/msm/
H A Dqcom,kpss-gcc.txt1 Krait Processor Sub-system (KPSS) Global Clock Controller (GCC)
5 - compatible:
9 "qcom,kpss-gcc" should also be included.
10 "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc"
11 "qcom,kpss-gcc-apq8064", "qcom,kpss-gcc"
12 "qcom,kpss-gcc-msm8974", "qcom,kpss-gcc"
13 "qcom,kpss-gcc-msm8960", "qcom,kpss-gcc"
15 - reg:
17 Value type: <prop-encoded-array>
20 - clocks:
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/freebsd/sys/contrib/device-tree/Bindings/slimbus/
H A Dqcom,slim.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
11 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
18 - $ref: slimbus.yaml#
23 - enum:
24 - qcom,apq8064-slim
25 - const: qcom,slim
29 - description: Physical address of controller register blocks
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H A Dslimbus.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
13 SLIMbus is a 2-wire bus, and is used to communicate with peripheral
14 components like audio-codec.
18 pattern: "^slim(@.*|-([0-9]|[1-9][0-9]+))?$"
20 "#address-cells":
23 "#size-cells":
27 "^.*@[0-9a-f]+,[0-9a-f]+$":
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/freebsd/sys/contrib/device-tree/Bindings/dma/
H A Dqcom_adm.txt4 - compatible: must contain "qcom,adm" for IPQ/APQ8064 and MSM8960
5 - reg: Address range for DMA registers
6 - interrupts: Should contain one interrupt shared by all channels
7 - #dma-cells: must be <2>. First cell denotes the channel number. Second cell
9 - clocks: Should contain the core clock and interface clock.
10 - clock-names: Must contain "core" for the core clock and "iface" for the
12 - resets: Must contain an entry for each entry in reset names.
13 - reset-names: Must include the following entries:
14 - clk
15 - c0
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H A Dqcom_bam_dma.txt4 - compatible: must be one of the following:
5 * "qcom,bam-v1.4.0" for MSM8974, APQ8074 and APQ8084
6 * "qcom,bam-v1.3.0" for APQ8064, IPQ8064 and MSM8960
7 * "qcom,bam-v1.7.0" for MSM8916
8 - reg: Address range for DMA registers
9 - interrupts: Should contain the one interrupt shared by all channels
10 - #dma-cells: must be <1>, the cell in the dmas property of the client device
12 - clocks: required clock
13 - clock-names: must contain "bam_clk" entry
14 - qcom,ee : indicates the active Execution Environment identifier (0-7) used in
[all …]
H A Dqcom,bam-dma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/qcom,bam-dm
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/freebsd/sys/contrib/device-tree/Bindings/nvmem/
H A Dqcom,qfprom.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
13 - $ref: nvmem.yaml#
14 - $ref: nvmem-deprecated-cells.yaml#
19 - enum:
20 - qcom,apq8064-qfprom
21 - qcom,apq8084-qfprom
22 - qcom,ipq5332-qfprom
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/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Dqcom-soc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/qcom-so
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/freebsd/sys/contrib/device-tree/Bindings/display/msm/
H A Ddsi-controller-main.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
15 - items:
16 - enum:
17 - qcom,apq8064-dsi-ctrl
18 - qcom,msm8226-dsi-ctrl
19 - qcom,msm8916-dsi-ctrl
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/freebsd/contrib/llvm-project/llvm/lib/TargetParser/
H A DHost.cpp1 //===-- Host.cpp - Implement OS Host Detection ------------------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
18 #include "llvm/Config/llvm-config.h"
25 // Include the platform-specific parts of this class.
54 #define DEBUG_TYPE "host-detection"
56 //===----------------------------------------------------------------------===//
60 //===----------------------------------------------------------------------===//
78 // and so we must use an operating-system interface to determine the current in getHostCPUNameForPowerPC()
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