| /linux/Documentation/devicetree/bindings/clock/ |
| H A D | gated-fixed-clock.yaml | 4 $id: http://devicetree.org/schemas/clock/gated-fixed-clock.yaml#
7 title: Gated Fixed clock
14 const: gated-fixed-clock
44 compatible = "gated-fixed-clock";
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| /linux/drivers/cpuidle/ |
| H A D | cpuidle-cps.c | 18 STATE_CLOCK_GATED, /* Core clock gated */
19 STATE_POWER_GATED, /* Core power gated */
86 .name = "clock-gated",
87 .desc = "core clock gated",
94 .name = "power-gated",
95 .desc = "core power gated",
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| /linux/sound/hda/common/ |
| H A D | jack.c | 214 /* If a jack is gated by this one update it. */ in jack_detect_update()
216 struct hda_jack_tbl *gated = in jack_detect_update() local
219 if (gated) { in jack_detect_update()
220 gated->jack_dirty = 1; in jack_detect_update()
221 jack_detect_update(codec, gated); in jack_detect_update()
378 * @gated_nid: gated pin NID
381 * Indicates the gated jack is only valid when the gating jack is plugged.
386 struct hda_jack_tbl *gated = snd_hda_jack_tbl_new(codec, gated_nid, 0); in snd_hda_jack_set_gating_jack() local
392 if (!gated || !gating) in snd_hda_jack_set_gating_jack()
395 gated->gating_jack = gating_nid; in snd_hda_jack_set_gating_jack()
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| /linux/drivers/gpu/drm/radeon/ |
| H A D | vce_v2_0.c | 39 static void vce_v2_0_set_sw_cg(struct radeon_device *rdev, bool gated) in vce_v2_0_set_sw_cg() argument
43 if (gated) { in vce_v2_0_set_sw_cg()
74 static void vce_v2_0_set_dyn_cg(struct radeon_device *rdev, bool gated) in vce_v2_0_set_dyn_cg() argument
80 if (gated) { in vce_v2_0_set_dyn_cg()
99 if (gated) in vce_v2_0_set_dyn_cg()
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| /linux/drivers/clk/ |
| H A D | clk-gpio.c | 23 * DOC: basic gpio gated clock which can be enabled and disabled
34 * struct clk_gpio - gpio gated clock
245 * DOC: gated fixed clock, controlled with a gpio output and a regulator
305 * Fixed gated clock with non-sleeping gpio.
342 * Fixed gated clock with non-sleeping gpio.
415 { .compatible = "gated-fixed-clock" },
422 .name = "gated-fixed-clk",
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| H A D | clk-gemini.c | 53 * struct gemini_gate_data - Gemini gated clocks
101 * not be gated off.
336 * These are the leaf gates, at boot no clocks are gated. in gemini_clk_probe()
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| /linux/arch/mips/bcm63xx/ |
| H A D | clk.c | 425 /* gated clocks */
443 /* gated clocks */
455 /* gated clocks */
469 /* gated clocks */
483 /* gated clocks */
499 /* gated clocks */
519 /* gated clocks */
534 /* gated clocks */
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| /linux/include/dt-bindings/clock/ |
| H A D | tegra234-clock.h | 81 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0 divider gated output */
83 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0 divider gated output */
87 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK divider gated output */
242 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SE switch divider gated output */
617 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SEU1 switch divider gated output */
675 /** @brief GBE_UPHY_MGBES_APP_CLK switch divider gated output */
691 /** @brief GBE_UPHY_MGBE0_TX_CLK divider gated output */
693 /** @brief GBE_UPHY_MGBE0_TX_PCS_CLK divider gated output */
705 /** @brief GBE_UPHY_MGBE0_PTP_REF_CLK divider gated output */
709 /** @brief GBE_UPHY_MGBE1_TX_CLK divider gated output */
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| /linux/tools/perf/pmu-events/arch/arm64/ampere/emag/ |
| H A D | clock.json | 7 "PublicDescription": "FSU clocking gated off cycle",
10 "BriefDescription": "FSU clocking gated off cycle"
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| /linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/ |
| H A D | smu_v12_0_ppsmc.h | 42 #define PPSMC_MSG_PowerDownIspByTile 0x9 // ISP is power gated by default
44 #define PPSMC_MSG_PowerDownVcn 0xB // VCN is power gated by default
46 #define PPSMC_MSG_PowerDownSdma 0xD // SDMA is power gated by default
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| H A D | smu_v13_0_4_ppsmc.h | 60 #define PPSMC_MSG_PowerUpVcn 0x07 ///< Power up VCN; VCN is power gated by defau…
90 #define PPSMC_MSG_PowerUpJpeg 0x22 ///< Power up Jpeg; VCN is power gated by defa…
98 #define PPSMC_MSG_PowerDownIspByTile 0x29 ///< ISP is power gated by default
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| H A D | smu_v13_0_5_ppsmc.h | 41 #define PPSMC_MSG_PowerUpVcn 6 ///< Power up VCN; VCN is power gated by default
54 #define PPSMC_MSG_PowerUpJpeg 19 ///< Power up Jpeg; VCN is power gated by default
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| H A D | smu_v11_5_ppsmc.h | 40 #define PPSMC_MSG_PowerDownIspByTile 0x6 // ISP is power gated by default
42 #define PPSMC_MSG_PowerDownVcn 0x8 // VCN is power gated by default
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| H A D | smu_v13_0_1_ppsmc.h | 51 #define PPSMC_MSG_PowerUpVcn 0x07 ///< Power up VCN; VCN is power gated by defau…
78 #define PPSMC_MSG_PowerUpJpeg 0x22 ///< Power up Jpeg; VCN is power gated by defa…
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| /linux/arch/mips/include/asm/ |
| H A D | pm-cps.h | 26 CPS_PM_CLOCK_GATED, /* Core clock gated */
27 CPS_PM_POWER_GATED, /* Core power gated */
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| /linux/arch/arm/mach-tegra/ |
| H A D | platsmp.c | 50 * power-gated via the flow controller). This will have no in tegra20_boot_secondary()
103 * The power status of the cold boot CPU is power gated as in tegra30_boot_secondary()
105 * be un-gated by un-toggling the power gate register in tegra30_boot_secondary()
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| /linux/drivers/mmc/host/ |
| H A D | toshsd.h | 14 #define SD_PCICFG_GATEDCLK 0x41 /* Gated clock */
22 #define SD_PCICFG_EXTGATECLK1 0xf0 /* Could be used for gated clock */
23 #define SD_PCICFG_EXTGATECLK2 0xf1 /* Could be used for gated clock */
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| /linux/drivers/clk/zynqmp/ |
| H A D | clk-zynqmp.h | 14 /* must be gated across rate change */
16 /* must be gated across re-parent */
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | vce_v2_0.c | 316 static void vce_v2_0_set_sw_cg(struct amdgpu_device *adev, bool gated) in vce_v2_0_set_sw_cg() argument
320 if (gated) { in vce_v2_0_set_sw_cg()
351 static void vce_v2_0_set_dyn_cg(struct amdgpu_device *adev, bool gated) in vce_v2_0_set_dyn_cg() argument
362 if (gated) { in vce_v2_0_set_dyn_cg()
385 if(gated) in vce_v2_0_set_dyn_cg()
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| /linux/drivers/clk/imx/ |
| H A D | clk-composite-7ulp.c | 130 * make sure clock is gated during clock tree initialization, in imx_ulp_clk_hw_composite()
131 * the HW ONLY allow clock parent/rate changed with clock gated, in imx_ulp_clk_hw_composite()
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| /linux/include/sound/ |
| H A D | soc-dai.h | 58 * DAI bit clocks can be gated (disabled) when the DAI is not
62 #define SND_SOC_DAIFMT_GATED (0 << 4) /* clock is gated */
66 * define GATED -> CONT. GATED will be selected if both are selected.
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| /linux/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | rockchip,rk3399-dmc.yaml | 100 self-refresh mode. The controller, pi, PHY and DRAM clock will be gated
313 self-refresh mode. The controller, pi, PHY and DRAM clock will be gated
332 sr-mc-gate-idle-dis-freq, the clock will not be gated when idle. See also
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| /linux/arch/arm/mach-omap2/ |
| H A D | mcbsp.c | 29 * Sidetone needs non-gated ICLK and sidetone autoidle is broken.
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| H A D | clkt2xxx_dpll.c | 25 * stop when its downstream clocks are gated. No return value.
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| /linux/arch/arm/mach-s3c/ |
| H A D | cpuidle-s3c64xx.c | 47 .desc = "System active, ARM gated",
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