Searched full:gateable (Results 1 – 15 of 15) sorted by relevance
19 by means of PLLs and gateable/non-gateable dividers embedded into the CCU.
19 by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The
7 title: Allwinner A10 Gateable Oscillator Clock
38 either gateable or ungateable. Some of the CCU dividers can be as well
8 Q: Why is the main 24MHz oscillator gateable? Wouldn't that break the
19 PM domain, and may have a gateable functional clock. Before a device
24 * CP110 has 32 gateable clocks, for the various peripherals in the IP.60 /* A number of gateable clocks need special handling */
246 pr_err("mvebu-clk-gating: cannot instantiate more than one gateable clock device\n"); in mvebu_clk_gating_setup()
19 * DOC: basic gateable clock which can gate and ungate its output
18 * DOC: basic gateable clock which can gate and ungate its output
255 * struct clk_gated_fixed - Gateable fixed rate clock
268 * device are gateable or not.
108 vice versa. To illustrate consider the simple gateable clk implementation in
877 u8 gate; /* is it independently gateable? */
765 gatable||gateable