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/linux/tools/testing/selftests/tc-testing/tc-tests/actions/
H A Dgate.json4 "name": "Add gate action with priority and sched-entry",
7 "gate"
14 "$TC action flush action gate",
20 … "cmdUnderTest": "$TC action add action gate priority 1 sched-entry close 100000000ns index 100",
22 "verifyCmd": "$TC action get action gate index 100",
26 "$TC action flush action gate"
31 "name": "Add gate action with base-time",
34 "gate"
41 "$TC actions flush action gate",
47 …"cmdUnderTest": "$TC action add action gate base-time 200000000000ns sched-entry close 100000000ns…
[all …]
/linux/drivers/clk/tegra/
H A Dclk-periph-gate.c18 /* Macros to assist peripheral gate clock */
19 #define read_enb(gate) \ argument
20 readl_relaxed(gate->clk_base + (gate->regs->enb_reg))
21 #define write_enb_set(val, gate) \ argument
22 writel_relaxed(val, gate->clk_base + (gate->regs->enb_set_reg))
23 #define write_enb_clr(val, gate) \ argument
24 writel_relaxed(val, gate->clk_base + (gate->regs->enb_clr_reg))
26 #define read_rst(gate) \ argument
27 readl_relaxed(gate->clk_base + (gate->regs->rst_reg))
28 #define write_rst_clr(val, gate) \ argument
[all …]
/linux/drivers/clk/samsung/
H A Dclk-exynos5433.c578 GATE(CLK_ACLK_G3D_400, "aclk_g3d_400", "div_aclk_g3d_400",
580 GATE(CLK_ACLK_IMEM_SSSX_266, "aclk_imem_sssx_266",
583 GATE(CLK_ACLK_BUS0_400, "aclk_bus0_400", "div_aclk_bus0_400",
586 GATE(CLK_ACLK_BUS1_400, "aclk_bus1_400", "div_aclk_bus1_400",
589 GATE(CLK_ACLK_IMEM_200, "aclk_imem_200", "div_aclk_imem_200",
592 GATE(CLK_ACLK_IMEM_266, "aclk_imem_266", "div_aclk_imem_266",
595 GATE(CLK_ACLK_PERIC_66, "aclk_peric_66", "div_aclk_peric_66_b",
598 GATE(CLK_ACLK_PERIS_66, "aclk_peris_66", "div_aclk_peris_66_b",
601 GATE(CLK_ACLK_MSCL_400, "aclk_mscl_400", "div_aclk_mscl_400",
604 GATE(CLK_ACLK_FSYS_200, "aclk_fsys_200", "div_aclk_fsys_200",
[all …]
H A Dclk-fsd.c260 GATE(0, "cmu_cis0_clkgate", "mout_cmu_cis0_clkmux", GAT_CMU_CIS0_CLKGATE, 21,
262 GATE(0, "cmu_cis1_clkgate", "mout_cmu_cis1_clkmux", GAT_CMU_CIS1_CLKGATE, 21,
264 GATE(0, "cmu_cis2_clkgate", "mout_cmu_cis2_clkmux", GAT_CMU_CIS2_CLKGATE, 21,
266 GATE(CMU_CPUCL_SWITCH_GATE, "cmu_cpucl_switch_gate", "mout_cmu_cpucl_switchmux",
268 GATE(GAT_CMU_FSYS0_SHARED0DIV4, "cmu_fsys0_shared0div4_gate", "dout_cmu_pll_shared0_div4",
270 GATE(0, "cmu_fsys0_shared1div4_clk", "dout_cmu_pll_shared1_div3",
272 GATE(0, "cmu_fsys0_shared1div4_gate", "dout_cmu_pll_shared1_div4",
274 GATE(0, "cmu_fsys1_shared0div4_gate", "mout_cmu_fsys1_aclk_mux",
276 GATE(0, "cmu_fsys1_shared1div4_gate", "dout_cmu_fsys1_shared0div4",
278 GATE(0, "cmu_imem_aclk_gate", "dout_cmu_pll_shared1_div9", GAT_CMU_IMEM_ACLK_GATE, 21,
[all …]
H A Dclk-exynos7870.c499 GATE(CLK_GOUT_MIF_CMU_DISPAUD_BUS, "gout_mif_cmu_dispaud_bus",
502 GATE(CLK_GOUT_MIF_CMU_DISPAUD_DECON_ECLK,
506 GATE(CLK_GOUT_MIF_CMU_DISPAUD_DECON_VCLK,
510 GATE(CLK_GOUT_MIF_CMU_FSYS_BUS, "gout_mif_cmu_fsys_bus",
513 GATE(CLK_GOUT_MIF_CMU_FSYS_MMC0, "gout_mif_cmu_fsys_mmc0",
516 GATE(CLK_GOUT_MIF_CMU_FSYS_MMC1, "gout_mif_cmu_fsys_mmc1",
519 GATE(CLK_GOUT_MIF_CMU_FSYS_MMC2, "gout_mif_cmu_fsys_mmc2",
522 GATE(CLK_GOUT_MIF_CMU_FSYS_USB20DRD_REFCLK,
527 GATE(CLK_GOUT_MIF_CMU_G3D_SWITCH, "gout_mif_cmu_g3d_switch",
530 GATE(CLK_GOUT_MIF_CMU_ISP_CAM, "gout_mif_cmu_isp_cam",
[all …]
H A Dclk-gs101.c1262 GATE(CLK_GOUT_CMU_BUS0_BOOST, "gout_cmu_bus0_boost",
1264 GATE(CLK_GOUT_CMU_BUS1_BOOST, "gout_cmu_bus1_boost",
1266 GATE(CLK_GOUT_CMU_BUS2_BOOST, "gout_cmu_bus2_boost",
1268 GATE(CLK_GOUT_CMU_CORE_BOOST, "gout_cmu_core_boost",
1270 GATE(CLK_GOUT_CMU_CPUCL0_BOOST, "gout_cmu_cpucl0_boost",
1273 GATE(CLK_GOUT_CMU_CPUCL1_BOOST, "gout_cmu_cpucl1_boost",
1276 GATE(CLK_GOUT_CMU_CPUCL2_BOOST, "gout_cmu_cpucl2_boost",
1279 GATE(CLK_GOUT_CMU_MIF_BOOST, "gout_cmu_mif_boost",
1282 GATE(CLK_GOUT_CMU_MIF_SWITCH, "gout_cmu_mif_switch",
1284 GATE(CLK_GOUT_CMU_BO_BUS, "gout_cmu_bo_bus", "mout_cmu_bo_bus",
[all …]
H A Dclk-exynos8895.c1108 GATE(CLK_GOUT_CMU_DROOPDETECTOR, "gout_droopdetector",
1111 GATE(CLK_GOUT_CMU_MIF_SWITCH, "gout_cmu_mif_switch",
1113 GATE(CLK_GOUT_CMU_ABOX_CPUABOX, "gout_cmu_abox_cpuabox",
1116 GATE(CLK_GOUT_CMU_APM_BUS, "gout_cmu_apm_bus", "mout_cmu_apm_bus",
1118 GATE(CLK_GOUT_CMU_BUS1_BUS, "gout_cmu_bus1_bus", "mout_cmu_bus1_bus",
1120 GATE(CLK_GOUT_CMU_BUSC_BUS, "gout_cmu_busc_bus", "mout_cmu_busc_bus",
1122 GATE(CLK_GOUT_CMU_BUSC_BUSPHSI2C, "gout_cmu_busc_busphsi2c",
1125 GATE(CLK_GOUT_CMU_CAM_BUS, "gout_cmu_cam_bus", "mout_cmu_cam_bus",
1127 GATE(CLK_GOUT_CMU_CAM_TPU0, "gout_cmu_cam_tpu0", "mout_cmu_cam_tpu0",
1129 GATE(CLK_GOUT_CMU_CAM_TPU1, "gout_cmu_cam_tpu1", "mout_cmu_cam_tpu1",
[all …]
H A Dclk-exynos3250.c441 GATE(CLK_ASYNC_G3D, "async_g3d", "div_aclk_100", GATE_IP_LEFTBUS, 6,
443 GATE(CLK_ASYNC_MFCL, "async_mfcl", "div_aclk_100", GATE_IP_LEFTBUS, 4,
445 GATE(CLK_PPMULEFT, "ppmuleft", "div_aclk_100", GATE_IP_LEFTBUS, 1,
447 GATE(CLK_GPIO_LEFT, "gpio_left", "div_aclk_100", GATE_IP_LEFTBUS, 0,
451 GATE(CLK_ASYNC_ISPMX, "async_ispmx", "div_aclk_100",
453 GATE(CLK_ASYNC_FSYSD, "async_fsysd", "div_aclk_100",
455 GATE(CLK_ASYNC_LCD0X, "async_lcd0x", "div_aclk_100",
457 GATE(CLK_ASYNC_CAMX, "async_camx", "div_aclk_100", GATE_IP_RIGHTBUS, 2,
459 GATE(CLK_PPMURIGHT, "ppmuright", "div_aclk_100", GATE_IP_RIGHTBUS, 1,
461 GATE(CLK_GPIO_RIGHT, "gpio_right", "div_aclk_100", GATE_IP_RIGHTBUS, 0,
[all …]
H A Dclk-exynos5250.c447 GATE(CLK_MDMA0, "mdma0", "div_aclk266", GATE_IP_ACP, 1, 0, 0),
448 GATE(CLK_SSS, "sss", "div_aclk266", GATE_IP_ACP, 2, 0, 0),
449 GATE(CLK_G2D, "g2d", "div_aclk200", GATE_IP_ACP, 3, 0, 0),
450 GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "div_aclk266", GATE_IP_ACP, 5, 0, 0),
455 GATE(CLK_SCLK_CAM_BAYER, "sclk_cam_bayer", "div_cam_bayer",
457 GATE(CLK_SCLK_CAM0, "sclk_cam0", "div_cam0",
459 GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1",
461 GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "div_gscl_wa",
463 GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "div_gscl_wb",
466 GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "div_fimd1",
[all …]
H A Dclk-exynos990.c1024 GATE(CLK_GOUT_CMU_APM_BUS, "gout_cmu_apm_bus", "mout_cmu_apm_bus",
1026 GATE(CLK_GOUT_CMU_AUD_CPU, "gout_cmu_aud_cpu", "mout_cmu_aud_cpu",
1028 GATE(CLK_GOUT_CMU_BUS0_BUS, "gout_cmu_bus0_bus", "mout_cmu_bus0_bus",
1030 GATE(CLK_GOUT_CMU_BUS1_BUS, "gout_cmu_bus1_bus", "mout_cmu_bus1_bus",
1032 GATE(CLK_GOUT_CMU_BUS1_SSS, "gout_cmu_bus1_sss", "mout_cmu_bus1_sss",
1034 GATE(CLK_GOUT_CMU_CIS_CLK0, "gout_cmu_cis_clk0", "mout_cmu_cis_clk0",
1036 GATE(CLK_GOUT_CMU_CIS_CLK1, "gout_cmu_cis_clk1", "mout_cmu_cis_clk1",
1038 GATE(CLK_GOUT_CMU_CIS_CLK2, "gout_cmu_cis_clk2", "mout_cmu_cis_clk2",
1040 GATE(CLK_GOUT_CMU_CIS_CLK3, "gout_cmu_cis_clk3", "mout_cmu_cis_clk3",
1042 GATE(CLK_GOUT_CMU_CIS_CLK4, "gout_cmu_cis_clk4", "mout_cmu_cis_clk4",
[all …]
/linux/drivers/clk/mmp/
H A Dclk-gate.c3 * mmp gate clock operation source file
26 struct mmp_clk_gate *gate = to_clk_mmp_gate(hw); in mmp_clk_gate_enable() local
31 if (gate->lock) in mmp_clk_gate_enable()
32 spin_lock_irqsave(gate->lock, flags); in mmp_clk_gate_enable()
34 tmp = readl(gate->reg); in mmp_clk_gate_enable()
35 tmp &= ~gate->mask; in mmp_clk_gate_enable()
36 tmp |= gate->val_enable; in mmp_clk_gate_enable()
37 writel(tmp, gate->reg); in mmp_clk_gate_enable()
39 if (gate->lock) in mmp_clk_gate_enable()
40 spin_unlock_irqrestore(gate->lock, flags); in mmp_clk_gate_enable()
[all …]
/linux/drivers/clk/imx/
H A Dclk-gate-93.c49 struct imx93_clk_gate *gate = to_imx93_clk_gate(hw); in imx93_clk_gate_do_hardware() local
52 val = readl(gate->reg + AUTHEN_OFFSET); in imx93_clk_gate_do_hardware()
55 writel(val, gate->reg + LPM_CUR_OFFSET); in imx93_clk_gate_do_hardware()
57 val = readl(gate->reg + DIRECT_OFFSET); in imx93_clk_gate_do_hardware()
58 val &= ~(gate->mask << gate->bit_idx); in imx93_clk_gate_do_hardware()
60 val |= (gate->val & gate->mask) << gate->bit_idx; in imx93_clk_gate_do_hardware()
61 writel(val, gate->reg + DIRECT_OFFSET); in imx93_clk_gate_do_hardware()
67 struct imx93_clk_gate *gate = to_imx93_clk_gate(hw); in imx93_clk_gate_enable() local
70 spin_lock_irqsave(gate->lock, flags); in imx93_clk_gate_enable()
72 if (gate->share_count && (*gate->share_count)++ > 0) in imx93_clk_gate_enable()
[all …]
H A Dclk-gate2.c19 * DOC: basic gateable clock which can gate and ungate its output
43 struct clk_gate2 *gate = to_clk_gate2(hw); in clk_gate2_do_shared_clks() local
46 reg = readl(gate->reg); in clk_gate2_do_shared_clks()
47 reg &= ~(gate->cgr_mask << gate->bit_idx); in clk_gate2_do_shared_clks()
49 reg |= (gate->cgr_val & gate->cgr_mask) << gate->bit_idx; in clk_gate2_do_shared_clks()
50 writel(reg, gate->reg); in clk_gate2_do_shared_clks()
55 struct clk_gate2 *gate = to_clk_gate2(hw); in clk_gate2_enable() local
58 spin_lock_irqsave(gate->lock, flags); in clk_gate2_enable()
60 if (gate->share_count && (*gate->share_count)++ > 0) in clk_gate2_enable()
65 spin_unlock_irqrestore(gate->lock, flags); in clk_gate2_enable()
[all …]
/linux/drivers/clk/
H A Dclk-gate.c18 * DOC: basic gateable clock which can gate and ungate its output
27 static inline u32 clk_gate_readl(struct clk_gate *gate) in clk_gate_readl() argument
29 if (gate->flags & CLK_GATE_BIG_ENDIAN) in clk_gate_readl()
30 return ioread32be(gate->reg); in clk_gate_readl()
32 return readl(gate->reg); in clk_gate_readl()
35 static inline void clk_gate_writel(struct clk_gate *gate, u32 val) in clk_gate_writel() argument
37 if (gate->flags & CLK_GATE_BIG_ENDIAN) in clk_gate_writel()
38 iowrite32be(val, gate->reg); in clk_gate_writel()
40 writel(val, gate->reg); in clk_gate_writel()
58 struct clk_gate *gate = to_clk_gate(hw); in clk_gate_endisable() local
[all …]
/linux/drivers/clk/rockchip/
H A Dclk-gate-grf.c29 struct rockchip_gate_grf *gate = to_gate_grf(hw); in rockchip_gate_grf_enable() local
30 u32 val = !(gate->flags & CLK_GATE_SET_TO_DISABLE) ? BIT(gate->shift) : 0; in rockchip_gate_grf_enable()
31 u32 hiword = ((gate->flags & CLK_GATE_HIWORD_MASK) ? 1 : 0) << (gate->shift + 16); in rockchip_gate_grf_enable()
34 ret = regmap_update_bits(gate->regmap, gate->reg, in rockchip_gate_grf_enable()
35 hiword | BIT(gate->shift), hiword | val); in rockchip_gate_grf_enable()
42 struct rockchip_gate_grf *gate = to_gate_grf(hw); in rockchip_gate_grf_disable() local
43 u32 val = !(gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : BIT(gate->shift); in rockchip_gate_grf_disable()
44 u32 hiword = ((gate->flags & CLK_GATE_HIWORD_MASK) ? 1 : 0) << (gate->shift + 16); in rockchip_gate_grf_disable()
46 regmap_update_bits(gate->regmap, gate->reg, in rockchip_gate_grf_disable()
47 hiword | BIT(gate->shift), hiword | val); in rockchip_gate_grf_disable()
[all …]
H A Dclk-rv1126b.c305 GATE(CLKOUT_PDM, "clkout_pdm", "clkout_pdm_src", 0,
346 GATE(HCLK_RKNN, "hclk_rknn", "clk_gpll_div8", CLK_IS_CRITICAL,
348 GATE(PCLK_NPU_ROOT, "pclk_npu_root", "clk_cpll_div10", CLK_IS_CRITICAL,
353 GATE(HCLK_VEPU_ROOT, "hclk_vepu_root", "clk_gpll_div8", CLK_IS_CRITICAL,
355 GATE(PCLK_VEPU_ROOT, "pclk_vepu_root", "clk_cpll_div10", 0,
366 GATE(HCLK_VI_ROOT, "hclk_vi_root", "clk_gpll_div8", CLK_IS_CRITICAL,
368 GATE(PCLK_VI_ROOT, "pclk_vi_root", "clk_cpll_div10", CLK_IS_CRITICAL,
382 GATE(HCLK_VDO_ROOT, "hclk_vdo_root", "clk_gpll_div8", CLK_IS_CRITICAL,
384 GATE(PCLK_VDO_ROOT, "pclk_vdo_root", "clk_cpll_div10", CLK_IS_CRITICAL,
392 GATE(DCLK_DECOM_SRC, "dclk_decom_src", "clk_gpll_div3", 0,
[all …]
H A Dclk-rk3368.c284 GATE(0, "apllb_core", "apllb", CLK_IGNORE_UNUSED,
286 GATE(0, "gpllb_core", "gpll", CLK_IGNORE_UNUSED,
289 GATE(0, "aplll_core", "aplll", CLK_IGNORE_UNUSED,
291 GATE(0, "gplll_core", "gpll", CLK_IGNORE_UNUSED,
308 GATE(0, "apllb_cs", "apllb", CLK_IGNORE_UNUSED,
310 GATE(0, "aplll_cs", "aplll", CLK_IGNORE_UNUSED,
312 GATE(0, "gpll_cs", "gpll", CLK_IGNORE_UNUSED,
323 GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0, RK3368_CLKGATE_CON(7), 10, GFLAGS),
325 GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
327 GATE(0, "gpll_ddr", "gpll", 0,
[all …]
H A Dclk-rk3399.c406 GATE(SCLK_USB2PHY0_REF, "clk_usb2phy0_ref", "xin24m", CLK_IGNORE_UNUSED,
408 GATE(SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", CLK_IGNORE_UNUSED,
411 GATE(0, "clk_usbphy0_480m_src", "clk_usbphy0_480m", 0,
413 GATE(0, "clk_usbphy1_480m_src", "clk_usbphy1_480m", 0,
428 GATE(ACLK_USB3_NOC, "aclk_usb3_noc", "aclk_usb3", CLK_IGNORE_UNUSED,
430 GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb3", 0,
432 GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb3", 0,
434 GATE(ACLK_USB3_RKSOC_AXI_PERF, "aclk_usb3_rksoc_axi_perf", "aclk_usb3", 0,
436 GATE(ACLK_USB3_GRF, "aclk_usb3_grf", "aclk_usb3", 0,
439 GATE(SCLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", 0,
[all …]
H A Dclk-rk3528.c310 GATE(SCLK_UART0, "sclk_uart0", "clk_uart0", 0,
320 GATE(SCLK_UART1, "sclk_uart1", "clk_uart1", 0,
330 GATE(SCLK_UART2, "sclk_uart2", "clk_uart2", 0,
340 GATE(SCLK_UART3, "sclk_uart3", "clk_uart3", 0,
350 GATE(SCLK_UART4, "sclk_uart4", "clk_uart4", 0,
360 GATE(SCLK_UART5, "sclk_uart5", "clk_uart5", 0,
370 GATE(SCLK_UART6, "sclk_uart6", "clk_uart6", 0,
380 GATE(SCLK_UART7, "sclk_uart7", "clk_uart7", 0,
390 GATE(MCLK_I2S0_2CH_SAI_SRC, "mclk_i2s0_2ch_sai_src", "mclk_i2s0_2ch_sai_src_pre", 0,
400 GATE(MCLK_I2S1_8CH_SAI_SRC, "mclk_i2s1_8ch_sai_src", "mclk_i2s1_8ch_sai_src_pre", 0,
[all …]
H A Dclk-rv1126.c284 GATE(CLK_WIFI_OSC0, "clk_wifi_osc0", "xin24m", 0,
289 GATE(PCLK_PMU, "pclk_pmu", "pclk_pdpmu", CLK_IGNORE_UNUSED,
292 GATE(PCLK_UART1, "pclk_uart1", "pclk_pdpmu", 0,
302 GATE(SCLK_UART1, "sclk_uart1", "sclk_uart1_mux", 0,
305 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_pdpmu", 0,
310 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_pdpmu", 0,
316 GATE(CLK_CAPTURE_PWM0, "clk_capture_pwm0", "xin24m", 0,
318 GATE(PCLK_PWM0, "pclk_pwm0", "pclk_pdpmu", 0,
323 GATE(CLK_CAPTURE_PWM1, "clk_capture_pwm1", "xin24m", 0,
325 GATE(PCLK_PWM1, "pclk_pwm1", "pclk_pdpmu", 0,
[all …]
H A Dclk-rk3228.c220 GATE(0, "apll_ddr", "apll", CLK_IGNORE_UNUSED,
222 GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
224 GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
229 GATE(0, "ddrc", "ddrphy_pre", CLK_IGNORE_UNUSED,
235 GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED,
237 GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
239 GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
257 GATE(0, "hdmiphy_aclk_cpu", "hdmiphy", CLK_IGNORE_UNUSED,
259 GATE(0, "gpll_aclk_cpu", "gpll", CLK_IGNORE_UNUSED,
261 GATE(0, "cpll_aclk_cpu", "cpll", CLK_IGNORE_UNUSED,
[all …]
H A Dclk-rv1108.c201 GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED,
203 GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
205 GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
213 GATE(ACLK_CORE, "aclk_core", "aclkenm_core", CLK_IGNORE_UNUSED,
215 GATE(0, "pclk_dbg", "pclken_dbg", CLK_IGNORE_UNUSED,
227 GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_rkvenc_pre", 0,
229 GATE(HCLK_RKVENC, "hclk_rkvenc", "hclk_rkvenc_pre", 0,
231 GATE(0, "aclk_rkvenc_niu", "aclk_rkvenc_pre", CLK_IGNORE_UNUSED,
233 GATE(0, "hclk_rkvenc_niu", "hclk_rkvenc_pre", CLK_IGNORE_UNUSED,
252 GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", 0,
[all …]
H A Dclk-rk3588.c787 GATE(PCLK_MIPI_DCPHY0, "pclk_mipi_dcphy0", "pclk_top_root", 0,
789 GATE(PCLK_MIPI_DCPHY1, "pclk_mipi_dcphy1", "pclk_top_root", 0,
791 GATE(PCLK_CSIPHY0, "pclk_csiphy0", "pclk_top_root", 0,
793 GATE(PCLK_CSIPHY1, "pclk_csiphy1", "pclk_top_root", 0,
795 GATE(PCLK_CRU, "pclk_cru", "pclk_top_root", CLK_IS_CRITICAL,
803 GATE(PCLK_BIGCORE0_PVTM, "pclk_bigcore0_pvtm", "pclk_bigcore0_root", 0,
805 GATE(CLK_BIGCORE0_PVTM, "clk_bigcore0_pvtm", "xin24m", 0,
807 GATE(CLK_CORE_BIGCORE0_PVTM, "clk_core_bigcore0_pvtm", "armclk_b01", 0,
815 GATE(PCLK_BIGCORE1_PVTM, "pclk_bigcore1_pvtm", "pclk_bigcore1_root", 0,
817 GATE(CLK_BIGCORE1_PVTM, "clk_bigcore1_pvtm", "xin24m", 0,
[all …]
H A Dclk-rk3328.c286 GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
288 GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
290 GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED,
292 GATE(0, "npll_core", "npll", CLK_IGNORE_UNUSED,
300 GATE(0, "aclk_core_niu", "aclk_core", 0,
302 GATE(0, "aclk_gic400", "aclk_core", CLK_IGNORE_UNUSED,
305 GATE(0, "clk_jtag", "jtag_clkin", CLK_IGNORE_UNUSED,
312 GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", CLK_SET_RATE_PARENT,
314 GATE(0, "aclk_gpu_niu", "aclk_gpu_pre", 0,
321 GATE(0, "clk_ddrmsch", "clk_ddr", CLK_IGNORE_UNUSED,
[all …]
/linux/drivers/clk/pistachio/
H A Dclk-pistachio.c19 GATE(CLK_MIPS, "mips", "mips_div", 0x104, 0),
20 GATE(CLK_AUDIO_IN, "audio_in", "audio_clk_in_gate", 0x104, 1),
21 GATE(CLK_AUDIO, "audio", "audio_div", 0x104, 2),
22 GATE(CLK_I2S, "i2s", "i2s_div", 0x104, 3),
23 GATE(CLK_SPDIF, "spdif", "spdif_div", 0x104, 4),
24 GATE(CLK_AUDIO_DAC, "audio_dac", "audio_dac_div", 0x104, 5),
25 GATE(CLK_RPU_V, "rpu_v", "rpu_v_div", 0x104, 6),
26 GATE(CLK_RPU_L, "rpu_l", "rpu_l_div", 0x104, 7),
27 GATE(CLK_RPU_SLEEP, "rpu_sleep", "rpu_sleep_div", 0x104, 8),
28 GATE(CLK_WIFI_PLL_GATE, "wifi_pll_gate", "wifi_pll_mux", 0x104, 9),
[all …]

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