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/linux/Documentation/userspace-api/media/v4l/
H A Dpixfmt-compressed.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
8 .. _compressed-formats:
18 .. flat-table:: Compressed Image Formats
19 :header-rows: 1
20 :stub-columns: 0
23 * - Identifier
24 - Code
25 - Details
26 * .. _V4L2-PIX-FMT-JPEG:
28 - ``V4L2_PIX_FMT_JPEG``
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H A Ddev-encoder.rst1 .. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
6 Memory-to-Memory Stateful Video Encoder Interface
12 further post-processing by the client.
34 5. Single-planar API (see :ref:`planar-apis`) and applicable structures may be
35 used interchangeably with multi-planar API, unless specified otherwise,
47 Refer to :ref:`decoder-glossary`.
52 .. kernel-render:: DOT
65 qi -> Initialization [ label = "open()" ];
67 Initialization -> Encoding [ label = "Both queues streaming" ];
69 Encoding -> Drain [ label = "V4L2_ENC_CMD_STOP" ];
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/linux/Documentation/networking/device_drivers/can/
H A Dcan327.rst1 .. SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
7 --------
14 -----------
26 -------------
29 into full fledged (as far as possible) CAN interfaces.
33 order to fake full-duplex operation.
36 enough to implement simple request-response protocols (such as OBD II),
50 -----------
59 ----------------------------------
68 --debug \
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/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac1000.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 Copyright (C) 2007-2009 STMicroelectronics Ltd
15 #define GMAC_FRAME_FILTER 0x00000004 /* Frame Filter */
23 #define GMAC_WAKEUP_FILTER 0x00000028 /* Wake-up Frame Filter */
79 #define GMAC_ADDR_HIGH(reg) ((reg > 15) ? 0x00000800 + (reg - 16) * 8 : \
81 #define GMAC_ADDR_LOW(reg) ((reg > 15) ? 0x00000804 + (reg - 16) * 8 : \
108 #define GMAC_CONTROL_BE 0x00200000 /* Frame Burst Enable */
109 #define GMAC_CONTROL_JE 0x00100000 /* Jumbo frame */
119 #define GMAC_CONTROL_LM 0x00001000 /* Loop-back mode */
132 /* GMAC Frame Filter defines */
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/linux/drivers/usb/dwc2/
H A Dhcd.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
3 * hcd.h - DesignWare HS OTG Controller host-mode declarations
5 * Copyright (C) 2004-2013 Synopsys, Inc.
24 * struct dwc2_host_chan - Software host channel descriptor
31 * - USB_SPEED_LOW
32 * - USB_SPEED_FULL
33 * - USB_SPEED_HIGH
35 * - USB_ENDPOINT_XFER_CONTROL: 0
36 * - USB_ENDPOINT_XFER_ISOC: 1
37 * - USB_ENDPOINT_XFER_BULK: 2
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/linux/drivers/firmware/tegra/
H A Divc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
47 * This structure is divided into two-cache aligned parts, the first is only
50 * lines, which is critical to performance and necessary in non-cache coherent
79 if (!ivc->peer) in tegra_ivc_invalidate()
82 dma_sync_single_for_cpu(ivc->peer, phys, TEGRA_IVC_ALIGN, in tegra_ivc_invalidate()
88 if (!ivc->peer) in tegra_ivc_flush()
91 dma_sync_single_for_device(ivc->peer, phys, TEGRA_IVC_ALIGN, in tegra_ivc_flush()
106 * Perform an over-full check to prevent denial of service attacks in tegra_ivc_empty()
109 * expected to check for full or over-full conditions. in tegra_ivc_empty()
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/linux/drivers/usb/c67x00/
H A Dc67x00-hcd.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * c67x00-hcd.h: Cypress C67X00 USB HCD
5 * Copyright (C) 2006-2008 Barco N.V.
37 * frames; there are 12000 bit times per frame.
43 #define MAX_FRAME_BW_STD (TOTAL_FRAME_BW - DEFAULT_EOT)
47 * Periodic transfers may only use 90% of the full frame, but as
48 * we currently don't even use 90% of the full frame, we may
49 * use the full usable time for periodic transfers.
53 /* -------------------------------------------------------------------------- */
89 return (struct c67x00_hcd *)(hcd->hcd_priv); in hcd_to_c67x00_hcd()
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/linux/drivers/net/ethernet/freescale/fs_enet/
H A Dfec.h1 /* SPDX-License-Identifier: GPL-2.0 */
13 #define FEC_ENET_TXF 0x08000000U /* Full frame transmitted */
15 #define FEC_ENET_RXF 0x02000000U /* Full frame received */
/linux/Documentation/networking/device_drivers/ethernet/dlink/
H A Ddl2k.rst1 .. SPDX-License-Identifier: GPL-2.0
4 D-Link DL2000-based Gigabit Ethernet Adapter Installation
11 - Compatibility List
12 - Quick Install
13 - Compiling the Driver
14 - Installing the Driver
15 - Option parameter
16 - Configuration Script Sample
17 - Troubleshooting
25 - D-Link DGE-550T Gigabit Ethernet Adapter.
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/linux/drivers/net/ethernet/freescale/
H A Dfec.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * fec.h -- Fast Ethernet Controller for Motorola ColdFire SoC
8 * (C) Copyright 2000-2005, Greg Ungerer (gerg@snapgear.com)
9 * (C) Copyright 2000-2001, Lineo (www.lineo.com)
23 #include <dt-bindings/firmware/imx/rsrc.h>
40 #define FEC_MII_DATA 0x040 /* MII manage frame reg */
70 #define FEC_R_FIFO_RSFL 0x190 /* Receive FIFO section full threshold */
73 #define FEC_R_FIFO_RAFL 0x19c /* Receive FIFO almost full threshold */
74 #define FEC_FTRL 0x1b0 /* Frame truncation receive length*/
161 #define FEC_MII_DATA 0x040 /* MII manage frame reg */
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/linux/Documentation/fb/
H A Dframebuffer.rst2 The Frame Buffer Device
9 ---------------
11 The frame buffer device provides an abstraction for the graphics hardware. It
12 represents the frame buffer of some video hardware and allows application
13 software to access the graphics hardware through a well-defined interface, so
14 the software doesn't need to know anything about the low-level (hardware
22 --------------------------
24 From the user's point of view, the frame buffer device looks just like any
26 specifies the frame buffer number.
31 0 = /dev/fb0 First frame buffer
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/linux/drivers/video/fbdev/
H A Dc2p_planar.c2 * Fast C2P (Chunky-to-Planar) Conversion
4 * Copyright (C) 2003-2008 Geert Uytterhoeven
21 * Perform a full C2P step on 32 8-bit pixels, stored in 8 32-bit words
23 * - 32 8-bit chunky pixels on input
24 * - permutated planar data (1 plane per 32-bit word) on output
45 * Store a full block of planar data after c2p conversion
74 * c2p_planar - Copy 8-bit chunky image data to a planar frame buffer
75 * @dst: Starting address of the planar frame buffer
80 * @dst_nextline: Frame buffer offset to the next line (in bytes)
81 * @dst_nextplane: Frame buffer offset to the next plane (in bytes)
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H A Dc2p_iplan2.c2 * Fast C2P (Chunky-to-Planar) Conversion
4 * Copyright (C) 2003-2008 Geert Uytterhoeven
21 * Perform a full C2P step on 16 8-bit pixels, stored in 4 32-bit words
23 * - 16 8-bit chunky pixels on input
24 * - permutated planar data (2 planes per 32-bit word) on output
45 * Store a full block of iplan2 data after c2p conversion
73 * c2p_iplan2 - Copy 8-bit chunky image data to an interleaved planar
74 * frame buffer with 2 bytes of interleave
75 * @dst: Starting address of the planar frame buffer
80 * @dst_nextline: Frame buffer offset to the next line (in bytes)
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/linux/drivers/gpu/drm/
H A Ddrm_debugfs_crc.c45 * DRM device drivers can provide to userspace CRC information of each frame as
49 * file dri/0/crtc-N/crc/control in debugfs, with N being the :ref:`index of
51 * driver-specific) and the "auto" keyword, which will let the driver select a
52 * default source of frame CRCs for this CRTC.
54 * Once frame CRC generation is enabled, userspace can capture them by reading
55 * the dri/0/crtc-N/crc/data file. Each line in that file contains the frame
58 * of CRC fields is source-specific.
61 * the frame contents as supplied by userspace (eDP 1.3), in general the CRC
62 * computation is performed in an unspecified way and on frame contents that have
64 * rely on being able to generate matching CRC values for the frame contents that
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/linux/drivers/net/fddi/skfp/h/
H A Dsupern_2.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
40 * FORMAC frame status (rx_msext)
47 #define FS_MSRABT (1<<14) /* frame was aborted during reception*/
48 #define FS_SSRCRTG (1<<12) /* if SA has set MSB (source-routing)*/
54 #define FS_SFRMTY2 (1<<6) /* frame-class bit */
55 #define FS_SFRMTY1 (1<<5) /* frame-type bit (impementor) */
56 #define FS_SFRMTY0 (1<<4) /* frame-type bit (LLC) */
58 #define FS_ERFBB0 (1<<0) /* - " - */
61 * status frame type
71 * bits in rx_descr.i (receive frame status word)
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/linux/drivers/gpu/drm/amd/amdgpu/
H A Ddce_v8_0.c82 (0x13830 - 0x7030) >> 2,
129 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); in dce_v8_0_audio_endpt_rreg()
132 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); in dce_v8_0_audio_endpt_rreg()
142 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); in dce_v8_0_audio_endpt_wreg()
145 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); in dce_v8_0_audio_endpt_wreg()
150 if (crtc >= adev->mode_info.num_crtc) in dce_v8_0_vblank_get_counter()
161 for (i = 0; i < adev->mode_info.num_crtc; i++) in dce_v8_0_pageflip_interrupt_init()
162 amdgpu_irq_get(adev, &adev->pageflip_irq, i); in dce_v8_0_pageflip_interrupt_init()
170 for (i = 0; i < adev->mode_info.num_crtc; i++) in dce_v8_0_pageflip_interrupt_fini()
171 amdgpu_irq_put(adev, &adev->pageflip_irq, i); in dce_v8_0_pageflip_interrupt_fini()
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H A Ddce_v11_0.c165 switch (adev->asic_type) { in dce_v11_0_init_golden_registers()
202 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); in dce_v11_0_audio_endpt_rreg()
205 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); in dce_v11_0_audio_endpt_rreg()
215 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); in dce_v11_0_audio_endpt_wreg()
218 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); in dce_v11_0_audio_endpt_wreg()
223 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) in dce_v11_0_vblank_get_counter()
234 for (i = 0; i < adev->mode_info.num_crtc; i++) in dce_v11_0_pageflip_interrupt_init()
235 amdgpu_irq_get(adev, &adev->pageflip_irq, i); in dce_v11_0_pageflip_interrupt_init()
243 for (i = 0; i < adev->mode_info.num_crtc; i++) in dce_v11_0_pageflip_interrupt_fini()
244 amdgpu_irq_put(adev, &adev->pageflip_irq, i); in dce_v11_0_pageflip_interrupt_fini()
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H A Ddce_v10_0.c150 switch (adev->asic_type) { in dce_v10_0_init_golden_registers()
178 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); in dce_v10_0_audio_endpt_rreg()
181 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); in dce_v10_0_audio_endpt_rreg()
191 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); in dce_v10_0_audio_endpt_wreg()
194 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); in dce_v10_0_audio_endpt_wreg()
199 if (crtc >= adev->mode_info.num_crtc) in dce_v10_0_vblank_get_counter()
210 for (i = 0; i < adev->mode_info.num_crtc; i++) in dce_v10_0_pageflip_interrupt_init()
211 amdgpu_irq_get(adev, &adev->pageflip_irq, i); in dce_v10_0_pageflip_interrupt_init()
219 for (i = 0; i < adev->mode_info.num_crtc; i++) in dce_v10_0_pageflip_interrupt_fini()
220 amdgpu_irq_put(adev, &adev->pageflip_irq, i); in dce_v10_0_pageflip_interrupt_fini()
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/linux/drivers/mailbox/
H A Dbcm-pdc-mailbox.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * offload engines. For example, the PDC driver works with both SPU-M and SPU2
41 #include <linux/mailbox/brcm-message.h>
43 #include <linux/dma-direction.h>
44 #include <linux/dma-mapping.h>
73 #define PREVTXD(i, max_mask) TXD((i) - 1, (max_mask))
75 #define PREVRXD(i, max_mask) RXD((i) - 1, (max_mask))
76 #define NTXDACTIVE(h, t, max_mask) TXD((t) - (h), (max_mask))
77 #define NRXDACTIVE(h, t, max_mask) RXD((t) - (h), (max_mask))
105 * before frame
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/linux/drivers/usb/host/
H A Duhci-hcd.c1 // SPDX-License-Identifier: GPL-2.0
8 * (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com
15 * support from usb-ohci.c by Adam Richter, adam@yggdrasil.com).
16 * (C) Copyright 1999 Gregory P. Smith (from usb-ohci.c)
17 * (C) Copyright 2004-2007 Alan Stern, stern@rowland.harvard.edu
40 #include <linux/dma-mapping.h>
50 #include "uhci-hcd.h"
97 * Calculate the link pointer DMA value for the first Skeleton QH in a frame.
99 static __hc32 uhci_frame_skel_link(struct uhci_hcd *uhci, int frame) in uhci_frame_skel_link() argument
105 * There's not much to be done about period-1 interrupts; they have in uhci_frame_skel_link()
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H A Dehci-sched.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2001-2004 by David Brownell
4 * Copyright (c) 2003 Michal Sojka, for high-speed iso transfers
7 /* this file is part of ehci-hcd.c */
9 /*-------------------------------------------------------------------------*/
21 * pre-calculated schedule data to make appending to the queue be quick.
27 * periodic_next_shadow - return "next" pointer on shadow list
37 return &periodic->qh->qh_next; in periodic_next_shadow()
39 return &periodic->fstn->fstn_next; in periodic_next_shadow()
41 return &periodic->itd->itd_next; in periodic_next_shadow()
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/linux/drivers/net/can/
H A Dcan327.c1 // SPDX-License-Identifier: GPL-2.0
7 * can327.c Author : Max Staudt <max-linux@enpas.org>
37 #include <linux/can/rx-offload.h>
53 /* Bits in elm->cmds_todo */
76 /* Per-channel lock */
101 /* The CAN frame and config the ELM327 is sending/using,
125 lockdep_assert_held(&elm->lock); in can327_send()
127 if (elm->uart_side_failure) in can327_send()
130 memcpy(elm->txbuf, buf, len); in can327_send()
134 * the transfer may be completed inside the ops->write() in can327_send()
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/linux/arch/x86/boot/
H A Dbioscall.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* -----------------------------------------------------------------------
4 * Copyright 2009-2014 Intel Corporation; author H. Peter Anvin
6 * ----------------------------------------------------------------------- */
18 /* Self-modify the INT instruction. Ugly, but works. */
30 /* Copy input state to stack frame */
37 /* Pop full state from the stack */
49 /* Push full state to the stack */
57 /* Re-establish C environment invariants */
64 /* Copy output state from stack frame */
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/linux/drivers/net/ethernet/oki-semi/pch_gbe/
H A Dpch_gbe.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 1999 - 2010 Intel Corporation.
26 * pch_gbe_regs_mac_adr - Structure holding values of mac address registers
35 * pch_udc_regs - Structure holding values of MAC registers
95 #define PCH_GBE_INT_RX_FRAME_ERR 0x00000004 /* Receive frame error */
113 #define PCH_GBE_MODE_FULL_DUPLEX 0x40000000 /* Duplex Mode [full duplex] */
114 #define PCH_GBE_MODE_FR_BST 0x04000000 /* Frame bursting is done */
145 /* Receive Almost Full Threshold */
208 /* Frame Start Threshold */
222 /* Transmit Almost Full Threshold */
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/linux/drivers/media/platform/mediatek/vcodec/decoder/vdec/
H A Dvdec_av1_req_lat_if.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <media/videobuf2-dma-contig.h>
22 #define AV1_REF_INVALID_SCALE -1
26 #define AV1_INVALID_IDX -1
39 (((_value_) < 0) ? -AV1_DIV_ROUND_UP_POW2(-(_value_), (_n_)) \
43 #define BIT_FLAG(x, bit) (!!((x)->flags & (bit)))
44 #define SEGMENTATION_FLAG(x, name) (!!((x)->flags & V4L2_AV1_SEGMENTATION_FLAG_##name))
45 #define QUANT_FLAG(x, name) (!!((x)->flags & V4L2_AV1_QUANTIZATION_FLAG_##name))
46 #define SEQUENCE_FLAG(x, name) (!!((x)->flags & V4L2_AV1_SEQUENCE_FLAG_##name))
47 #define FH_FLAG(x, name) (!!((x)->flags & V4L2_AV1_FRAME_FLAG_##name))
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