Lines Matching +full:full +full:- +full:frame
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
47 * This structure is divided into two-cache aligned parts, the first is only
50 * lines, which is critical to performance and necessary in non-cache coherent
79 if (!ivc->peer) in tegra_ivc_invalidate()
82 dma_sync_single_for_cpu(ivc->peer, phys, TEGRA_IVC_ALIGN, in tegra_ivc_invalidate()
88 if (!ivc->peer) in tegra_ivc_flush()
91 dma_sync_single_for_device(ivc->peer, phys, TEGRA_IVC_ALIGN, in tegra_ivc_flush()
106 * Perform an over-full check to prevent denial of service attacks in tegra_ivc_empty()
109 * expected to check for full or over-full conditions. in tegra_ivc_empty()
115 if (tx - rx > ivc->num_frames) in tegra_ivc_empty()
128 * capacity also appear full. in tegra_ivc_full()
130 return tx - rx >= ivc->num_frames; in tegra_ivc_full()
140 * over-full situation can lead to denial of service attacks. See the in tegra_ivc_available()
142 * over-full considerations. in tegra_ivc_available()
144 return tx - rx; in tegra_ivc_available()
149 unsigned int count = tegra_ivc_header_read_field(&ivc->tx.map, tx.count); in tegra_ivc_advance_tx()
151 tegra_ivc_header_write_field(&ivc->tx.map, tx.count, count + 1); in tegra_ivc_advance_tx()
153 if (ivc->tx.position == ivc->num_frames - 1) in tegra_ivc_advance_tx()
154 ivc->tx.position = 0; in tegra_ivc_advance_tx()
156 ivc->tx.position++; in tegra_ivc_advance_tx()
161 unsigned int count = tegra_ivc_header_read_field(&ivc->rx.map, rx.count); in tegra_ivc_advance_rx()
163 tegra_ivc_header_write_field(&ivc->rx.map, rx.count, count + 1); in tegra_ivc_advance_rx()
165 if (ivc->rx.position == ivc->num_frames - 1) in tegra_ivc_advance_rx()
166 ivc->rx.position = 0; in tegra_ivc_advance_rx()
168 ivc->rx.position++; in tegra_ivc_advance_rx()
177 * tx.channel->state is set locally, so it is not synchronized with in tegra_ivc_check_read()
181 * asynchronous transition of rx.channel->state to in tegra_ivc_check_read()
184 state = tegra_ivc_header_read_field(&ivc->tx.map, tx.state); in tegra_ivc_check_read()
186 return -ECONNRESET; in tegra_ivc_check_read()
193 * empty or full. in tegra_ivc_check_read()
195 if (!tegra_ivc_empty(ivc, &ivc->rx.map)) in tegra_ivc_check_read()
198 tegra_ivc_invalidate(ivc, ivc->rx.phys + offset); in tegra_ivc_check_read()
200 if (tegra_ivc_empty(ivc, &ivc->rx.map)) in tegra_ivc_check_read()
201 return -ENOSPC; in tegra_ivc_check_read()
211 state = tegra_ivc_header_read_field(&ivc->tx.map, tx.state); in tegra_ivc_check_write()
213 return -ECONNRESET; in tegra_ivc_check_write()
215 if (!tegra_ivc_full(ivc, &ivc->tx.map)) in tegra_ivc_check_write()
218 tegra_ivc_invalidate(ivc, ivc->tx.phys + offset); in tegra_ivc_check_write()
220 if (tegra_ivc_full(ivc, &ivc->tx.map)) in tegra_ivc_check_write()
221 return -ENOSPC; in tegra_ivc_check_write()
227 unsigned int frame, struct iosys_map *map) in tegra_ivc_frame_virt() argument
229 size_t offset = sizeof(struct tegra_ivc_header) + ivc->frame_size * frame; in tegra_ivc_frame_virt()
231 if (WARN_ON(frame >= ivc->num_frames)) in tegra_ivc_frame_virt()
232 return -EINVAL; in tegra_ivc_frame_virt()
241 unsigned int frame) in tegra_ivc_frame_phys() argument
245 offset = sizeof(struct tegra_ivc_header) + ivc->frame_size * frame; in tegra_ivc_frame_phys()
252 unsigned int frame, in tegra_ivc_invalidate_frame() argument
256 if (!ivc->peer || WARN_ON(frame >= ivc->num_frames)) in tegra_ivc_invalidate_frame()
259 phys = tegra_ivc_frame_phys(ivc, phys, frame) + offset; in tegra_ivc_invalidate_frame()
261 dma_sync_single_for_cpu(ivc->peer, phys, size, DMA_FROM_DEVICE); in tegra_ivc_invalidate_frame()
266 unsigned int frame, in tegra_ivc_flush_frame() argument
270 if (!ivc->peer || WARN_ON(frame >= ivc->num_frames)) in tegra_ivc_flush_frame()
273 phys = tegra_ivc_frame_phys(ivc, phys, frame) + offset; in tegra_ivc_flush_frame()
275 dma_sync_single_for_device(ivc->peer, phys, size, DMA_TO_DEVICE); in tegra_ivc_flush_frame()
278 /* directly peek at the next frame rx'ed */
284 return -EINVAL; in tegra_ivc_read_get_next_frame()
291 * Order observation of ivc->rx.position potentially indicating new in tegra_ivc_read_get_next_frame()
296 tegra_ivc_invalidate_frame(ivc, ivc->rx.phys, ivc->rx.position, 0, in tegra_ivc_read_get_next_frame()
297 ivc->frame_size); in tegra_ivc_read_get_next_frame()
299 return tegra_ivc_frame_virt(ivc, &ivc->rx.map, ivc->rx.position, map); in tegra_ivc_read_get_next_frame()
311 * have already observed the channel non-empty. This check is just to in tegra_ivc_read_advance()
320 tegra_ivc_flush(ivc, ivc->rx.phys + rx); in tegra_ivc_read_advance()
323 * Ensure our write to ivc->rx.position occurs before our read from in tegra_ivc_read_advance()
324 * ivc->tx.position. in tegra_ivc_read_advance()
329 * Notify only upon transition from full to non-full. The available in tegra_ivc_read_advance()
331 * side-effect will be a spurious notification. in tegra_ivc_read_advance()
333 tegra_ivc_invalidate(ivc, ivc->rx.phys + tx); in tegra_ivc_read_advance()
335 if (tegra_ivc_available(ivc, &ivc->rx.map) == ivc->num_frames - 1) in tegra_ivc_read_advance()
336 ivc->notify(ivc, ivc->notify_data); in tegra_ivc_read_advance()
342 /* directly poke at the next frame to be tx'ed */
351 return tegra_ivc_frame_virt(ivc, &ivc->tx.map, ivc->tx.position, map); in tegra_ivc_write_get_next_frame()
366 tegra_ivc_flush_frame(ivc, ivc->tx.phys, ivc->tx.position, 0, in tegra_ivc_write_advance()
367 ivc->frame_size); in tegra_ivc_write_advance()
370 * Order any possible stores to the frame before update of in tegra_ivc_write_advance()
371 * ivc->tx.position. in tegra_ivc_write_advance()
376 tegra_ivc_flush(ivc, ivc->tx.phys + tx); in tegra_ivc_write_advance()
379 * Ensure our write to ivc->tx.position occurs before our read from in tegra_ivc_write_advance()
380 * ivc->rx.position. in tegra_ivc_write_advance()
385 * Notify only upon transition from empty to non-empty. The available in tegra_ivc_write_advance()
387 * side-effect will be a spurious notification. in tegra_ivc_write_advance()
389 tegra_ivc_invalidate(ivc, ivc->tx.phys + rx); in tegra_ivc_write_advance()
391 if (tegra_ivc_available(ivc, &ivc->tx.map) == 1) in tegra_ivc_write_advance()
392 ivc->notify(ivc, ivc->notify_data); in tegra_ivc_write_advance()
402 tegra_ivc_header_write_field(&ivc->tx.map, tx.state, TEGRA_IVC_STATE_SYNC); in tegra_ivc_reset()
403 tegra_ivc_flush(ivc, ivc->tx.phys + offset); in tegra_ivc_reset()
404 ivc->notify(ivc, ivc->notify_data); in tegra_ivc_reset()
410 * IVC State Transition Table - see tegra_ivc_notified()
414 * ----- ------ -----------------------------------
434 tegra_ivc_invalidate(ivc, ivc->rx.phys + offset); in tegra_ivc_notified()
435 rx_state = tegra_ivc_header_read_field(&ivc->rx.map, tx.state); in tegra_ivc_notified()
436 tx_state = tegra_ivc_header_read_field(&ivc->tx.map, tx.state); in tegra_ivc_notified()
452 tegra_ivc_header_write_field(&ivc->tx.map, tx.count, 0); in tegra_ivc_notified()
453 tegra_ivc_header_write_field(&ivc->rx.map, rx.count, 0); in tegra_ivc_notified()
455 ivc->tx.position = 0; in tegra_ivc_notified()
456 ivc->rx.position = 0; in tegra_ivc_notified()
468 tegra_ivc_header_write_field(&ivc->tx.map, tx.state, TEGRA_IVC_STATE_ACK); in tegra_ivc_notified()
469 tegra_ivc_flush(ivc, ivc->tx.phys + offset); in tegra_ivc_notified()
474 ivc->notify(ivc, ivc->notify_data); in tegra_ivc_notified()
491 tegra_ivc_header_write_field(&ivc->tx.map, tx.count, 0); in tegra_ivc_notified()
492 tegra_ivc_header_write_field(&ivc->rx.map, rx.count, 0); in tegra_ivc_notified()
494 ivc->tx.position = 0; in tegra_ivc_notified()
495 ivc->rx.position = 0; in tegra_ivc_notified()
508 tegra_ivc_header_write_field(&ivc->tx.map, tx.state, TEGRA_IVC_STATE_ESTABLISHED); in tegra_ivc_notified()
509 tegra_ivc_flush(ivc, ivc->tx.phys + offset); in tegra_ivc_notified()
514 ivc->notify(ivc, ivc->notify_data); in tegra_ivc_notified()
532 tegra_ivc_header_write_field(&ivc->tx.map, tx.state, TEGRA_IVC_STATE_ESTABLISHED); in tegra_ivc_notified()
533 tegra_ivc_flush(ivc, ivc->tx.phys + offset); in tegra_ivc_notified()
538 ivc->notify(ivc, ivc->notify_data); in tegra_ivc_notified()
550 return -EAGAIN; in tegra_ivc_notified()
565 pr_err("%s: queue_size (%u) must be %u-byte aligned\n", in tegra_ivc_total_queue_size()
586 return -EINVAL; in tegra_ivc_check_params()
590 pr_err("frame size not adequately aligned: %zu\n", frame_size); in tegra_ivc_check_params()
591 return -EINVAL; in tegra_ivc_check_params()
600 return -EINVAL; in tegra_ivc_check_params()
605 return -EINVAL; in tegra_ivc_check_params()
612 return -EINVAL; in tegra_ivc_check_params()
618 return -EINVAL; in tegra_ivc_check_params()
632 if (map->is_iomem) in iosys_map_get_address()
633 return (unsigned long)map->vaddr_iomem; in iosys_map_get_address()
635 return (unsigned long)map->vaddr; in iosys_map_get_address()
640 if (WARN_ON(map->is_iomem)) in iosys_map_get_vaddr()
643 return map->vaddr; in iosys_map_get_vaddr()
656 return -EINVAL; in tegra_ivc_init()
663 return -E2BIG; in tegra_ivc_init()
673 ivc->rx.phys = dma_map_single(peer, iosys_map_get_vaddr(rx), queue_size, in tegra_ivc_init()
675 if (dma_mapping_error(peer, ivc->rx.phys)) in tegra_ivc_init()
676 return -ENOMEM; in tegra_ivc_init()
678 ivc->tx.phys = dma_map_single(peer, iosys_map_get_vaddr(tx), queue_size, in tegra_ivc_init()
680 if (dma_mapping_error(peer, ivc->tx.phys)) { in tegra_ivc_init()
681 dma_unmap_single(peer, ivc->rx.phys, queue_size, in tegra_ivc_init()
683 return -ENOMEM; in tegra_ivc_init()
686 ivc->rx.phys = rx_phys; in tegra_ivc_init()
687 ivc->tx.phys = tx_phys; in tegra_ivc_init()
690 iosys_map_copy(&ivc->rx.map, rx); in tegra_ivc_init()
691 iosys_map_copy(&ivc->tx.map, tx); in tegra_ivc_init()
692 ivc->peer = peer; in tegra_ivc_init()
693 ivc->notify = notify; in tegra_ivc_init()
694 ivc->notify_data = data; in tegra_ivc_init()
695 ivc->frame_size = frame_size; in tegra_ivc_init()
696 ivc->num_frames = num_frames; in tegra_ivc_init()
702 ivc->tx.position = 0; in tegra_ivc_init()
703 ivc->rx.position = 0; in tegra_ivc_init()
711 if (ivc->peer) { in tegra_ivc_cleanup()
712 size_t size = tegra_ivc_total_queue_size(ivc->num_frames * in tegra_ivc_cleanup()
713 ivc->frame_size); in tegra_ivc_cleanup()
715 dma_unmap_single(ivc->peer, ivc->rx.phys, size, in tegra_ivc_cleanup()
717 dma_unmap_single(ivc->peer, ivc->tx.phys, size, in tegra_ivc_cleanup()