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/linux/Documentation/devicetree/bindings/phy/
H A Dsamsung,exynos-pcie-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/samsung,exynos-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marek Szyprowski <m.szyprowski@samsung.com>
11 - Jaehoon Chung <jh80.chung@samsung.com>
14 "#phy-cells":
18 const: samsung,exynos5433-pcie-phy
23 samsung,pmu-syscon:
28 samsung,fsys-sysreg:
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/linux/Documentation/devicetree/bindings/soc/samsung/
H A Dsamsung,exynos-sysreg.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/soc/samsung/samsung,exynos-sysreg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC series System Registers (SYSREG)
10 - Krzysztof Kozlowski <krzk@kernel.org>
15 - items:
16 - enum:
17 - google,gs101-apm-sysreg
18 - google,gs101-hsi2-sysreg
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/linux/drivers/phy/samsung/
H A Dphy-exynos-pcie.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * Copyright (C) 2017-2020 Samsung Electronics Co., Ltd.
20 /* Sysreg FSYS register offsets and bits for Exynos5433 */
54 regmap_update_bits(ep->pmureg, EXYNOS5433_PMU_PCIE_PHY_OFFSET, in exynos5433_pcie_phy_init()
56 regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_GLOBAL_RESET, in exynos5433_pcie_phy_init()
58 regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_L1SUB_CM_CON, in exynos5433_pcie_phy_init()
61 regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_COMMON_RESET, in exynos5433_pcie_phy_init()
63 regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_MAC_RESET, in exynos5433_pcie_phy_init()
67 regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_GLOBAL_RESET, in exynos5433_pcie_phy_init()
69 regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_GLOBAL_RESET, in exynos5433_pcie_phy_init()
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/linux/arch/arm64/boot/dts/exynos/
H A Dexynos5433.dtsi1 // SPDX-License-Identifier: GPL-2.0
16 #include <dt-bindings/clock/exynos5433.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
21 #address-cells = <2>;
22 #size-cells = <2>;
24 interrupt-parent = <&gic>;
26 arm-a53-pmu {
27 compatible = "arm,cortex-a53-pmu";
32 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
35 arm-a57-pmu {
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/linux/arch/arm/boot/dts/samsung/
H A Dexynos3250.dtsi1 // SPDX-License-Identifier: GPL-2.0
17 #include "exynos4-cpu-thermal.dtsi"
18 #include <dt-bindings/clock/exynos3250.h>
19 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 #include <dt-bindings/interrupt-controller/irq.h>
24 interrupt-parent = <&gic>;
25 #address-cells = <1>;
26 #size-cells = <1>;
46 bus_dmc: bus-dmc {
47 compatible = "samsung,exynos-bus";
[all …]
H A Dexynos4x12.dtsi1 // SPDX-License-Identifier: GPL-2.0
19 #include "exynos4-cpu-thermal.dtsi"
27 fimc-lite0 = &fimc_lite_0;
28 fimc-lite1 = &fimc_lite_1;
31 bus_acp: bus-acp {
32 compatible = "samsung,exynos-bus";
34 clock-names = "bus";
35 operating-points-v2 = <&bus_acp_opp_table>;
38 bus_acp_opp_table: opp-table {
39 compatible = "operating-points-v2";
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H A Dexynos5420.dtsi1 // SPDX-License-Identifier: GPL-2.0
14 #include <dt-bindings/clock/exynos5420.h>
15 #include <dt-bindings/clock/exynos-audss-clk.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
37 bus_disp1: bus-disp1 {
38 compatible = "samsung,exynos-bus";
40 clock-names = "bus";
44 bus_disp1_fimd: bus-disp1-fimd {
45 compatible = "samsung,exynos-bus";
47 clock-names = "bus";
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/linux/drivers/ufs/host/
H A Dufs-exynos.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2014-2015 Samsung Electronics Co., Ltd.
13 #include <linux/arm-smccc.h>
25 #include "ufshcd-pltfrm.h"
29 #include "ufs-exynos.h"
95 /* FSYS UFS Shareability */
101 /* Multi-host registers */
210 if (ufs->sysreg) { in exynos_ufs_shareability()
211 return regmap_update_bits(ufs->sysreg, in exynos_ufs_shareability()
212 ufs->shareability_reg_offset, in exynos_ufs_shareability()
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/linux/drivers/clk/samsung/
H A Dclk-exynos5420.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <dt-bindings/clock/exynos5420.h>
12 #include <linux/clk-provider.h>
18 #include "clk-cpu.h"
19 #include "clk-exynos5-subcmu.h"
746 /* FSYS Block */
897 /* Audio - I2S */
904 /* SPI Pre-Ratio */
1036 /* FSYS Block */
1113 GATE(CLK_SYSREG, "sysreg", "aclk66_psgen",
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H A Dclk-exynos5433.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk-provider.h>
17 #include <dt-bindings/clock/exynos5433.h>
20 #include "clk-cpu.h"
21 #include "clk-exynos-arm64.h"
22 #include "clk-pll.h"
792 PLL_36XX_RATE(24 * MHZ, 393216003U, 197, 3, 2, -25690),
794 PLL_36XX_RATE(24 * MHZ, 368639991U, 246, 4, 2, -15729),
795 PLL_36XX_RATE(24 * MHZ, 361507202U, 181, 3, 2, -16148),
796 PLL_36XX_RATE(24 * MHZ, 338687988U, 113, 2, 2, -6816),
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