Lines Matching +full:fsys +full:- +full:sysreg
1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2014-2015 Samsung Electronics Co., Ltd.
13 #include <linux/arm-smccc.h>
25 #include "ufshcd-pltfrm.h"
29 #include "ufs-exynos.h"
95 /* FSYS UFS Shareability */
101 /* Multi-host registers */
210 if (ufs->sysreg) { in exynos_ufs_shareability()
211 return regmap_update_bits(ufs->sysreg, in exynos_ufs_shareability()
212 ufs->shareability_reg_offset, in exynos_ufs_shareability()
221 struct ufs_hba *hba = ufs->hba; in gs101_ufs_drv_init()
225 hba->caps |= UFSHCD_CAP_WB_EN; in gs101_ufs_drv_init()
228 hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; in gs101_ufs_drv_init()
244 struct ufs_hba *hba = ufs->hba; in exynosauto_ufs_post_hce_enable()
258 struct ufs_hba *hba = ufs->hba; in exynosauto_ufs_pre_link()
262 rx_line_reset_period = (RX_LINE_RESET_TIME * ufs->mclk_rate) / NSEC_PER_MSEC; in exynosauto_ufs_pre_link()
263 tx_line_reset_period = (TX_LINE_RESET_TIME * ufs->mclk_rate) / NSEC_PER_MSEC; in exynosauto_ufs_pre_link()
268 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); in exynosauto_ufs_pre_link()
285 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); in exynosauto_ufs_pre_link()
313 struct ufs_hba *hba = ufs->hba; in exynosauto_ufs_pre_pwr_change()
326 struct ufs_hba *hba = ufs->hba; in exynosauto_ufs_post_pwr_change()
339 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; in exynos7_ufs_pre_link()
340 u32 val = attr->pa_dbg_opt_suite1_val; in exynos7_ufs_pre_link()
341 struct ufs_hba *hba = ufs->hba; in exynos7_ufs_pre_link()
358 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off), in exynos7_ufs_pre_link()
364 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off), val); in exynos7_ufs_pre_link()
371 struct ufs_hba *hba = ufs->hba; in exynos7_ufs_post_link()
401 struct ufs_hba *hba = ufs->hba; in exynos7_ufs_post_pwr_change()
402 int lanes = max_t(u32, pwr->lane_rx, pwr->lane_tx); in exynos7_ufs_post_pwr_change()
416 * exynos_ufs_auto_ctrl_hcc - HCI core clock control by h/w
418 * - Before host controller S/W reset
419 * - Access to UFS protector's register
447 struct ufs_hba *hba = ufs->hba; in exynos_ufs_get_clk_info()
448 struct list_head *head = &hba->clk_list_head; in exynos_ufs_get_clk_info()
459 if (!IS_ERR(clki->clk)) { in exynos_ufs_get_clk_info()
460 if (!strcmp(clki->name, "core_clk")) in exynos_ufs_get_clk_info()
461 ufs->clk_hci_core = clki->clk; in exynos_ufs_get_clk_info()
462 else if (!strcmp(clki->name, "sclk_unipro_main")) in exynos_ufs_get_clk_info()
463 ufs->clk_unipro_main = clki->clk; in exynos_ufs_get_clk_info()
467 if (!ufs->clk_hci_core || !ufs->clk_unipro_main) { in exynos_ufs_get_clk_info()
468 dev_err(hba->dev, "failed to get clk info\n"); in exynos_ufs_get_clk_info()
469 ret = -EINVAL; in exynos_ufs_get_clk_info()
473 ufs->mclk_rate = clk_get_rate(ufs->clk_unipro_main); in exynos_ufs_get_clk_info()
474 pclk_rate = clk_get_rate(ufs->clk_hci_core); in exynos_ufs_get_clk_info()
475 f_min = ufs->pclk_avail_min; in exynos_ufs_get_clk_info()
476 f_max = ufs->pclk_avail_max; in exynos_ufs_get_clk_info()
478 if (ufs->opts & EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL) { in exynos_ufs_get_clk_info()
489 dev_err(hba->dev, "not available pclk range %lu\n", pclk_rate); in exynos_ufs_get_clk_info()
490 ret = -EINVAL; in exynos_ufs_get_clk_info()
494 ufs->pclk_rate = pclk_rate; in exynos_ufs_get_clk_info()
495 ufs->pclk_div = div; in exynos_ufs_get_clk_info()
503 if (ufs->opts & EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL) { in exynos_ufs_set_unipro_pclk_div()
507 hci_writel(ufs, UNIPRO_APB_CLK(val, ufs->pclk_div), in exynos_ufs_set_unipro_pclk_div()
514 struct ufs_hba *hba = ufs->hba; in exynos_ufs_set_pwm_clk_div()
515 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; in exynos_ufs_set_pwm_clk_div()
518 UIC_ARG_MIB(CMN_PWM_CLK_CTRL), attr->cmn_pwm_clk_ctrl); in exynos_ufs_set_pwm_clk_div()
523 struct ufs_hba *hba = ufs->hba; in exynos_ufs_calc_pwm_clk_div()
524 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; in exynos_ufs_calc_pwm_clk_div()
530 int i = 0, clk_idx = -1; in exynos_ufs_calc_pwm_clk_div()
543 if (clk_idx == -1) { in exynos_ufs_calc_pwm_clk_div()
545 dev_err(hba->dev, in exynos_ufs_calc_pwm_clk_div()
549 attr->cmn_pwm_clk_ctrl = clk_idx & PWM_CLK_CTRL_MASK; in exynos_ufs_calc_pwm_clk_div()
555 long pclk_rate = ufs->pclk_rate; in exynos_ufs_calc_time_cntr()
566 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; in exynos_ufs_specify_phy_time_attr()
567 struct ufs_phy_time_cfg *t_cfg = &ufs->t_cfg; in exynos_ufs_specify_phy_time_attr()
569 if (ufs->opts & EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR) in exynos_ufs_specify_phy_time_attr()
572 t_cfg->tx_linereset_p = in exynos_ufs_specify_phy_time_attr()
573 exynos_ufs_calc_time_cntr(ufs, attr->tx_dif_p_nsec); in exynos_ufs_specify_phy_time_attr()
574 t_cfg->tx_linereset_n = in exynos_ufs_specify_phy_time_attr()
575 exynos_ufs_calc_time_cntr(ufs, attr->tx_dif_n_nsec); in exynos_ufs_specify_phy_time_attr()
576 t_cfg->tx_high_z_cnt = in exynos_ufs_specify_phy_time_attr()
577 exynos_ufs_calc_time_cntr(ufs, attr->tx_high_z_cnt_nsec); in exynos_ufs_specify_phy_time_attr()
578 t_cfg->tx_base_n_val = in exynos_ufs_specify_phy_time_attr()
579 exynos_ufs_calc_time_cntr(ufs, attr->tx_base_unit_nsec); in exynos_ufs_specify_phy_time_attr()
580 t_cfg->tx_gran_n_val = in exynos_ufs_specify_phy_time_attr()
581 exynos_ufs_calc_time_cntr(ufs, attr->tx_gran_unit_nsec); in exynos_ufs_specify_phy_time_attr()
582 t_cfg->tx_sleep_cnt = in exynos_ufs_specify_phy_time_attr()
583 exynos_ufs_calc_time_cntr(ufs, attr->tx_sleep_cnt); in exynos_ufs_specify_phy_time_attr()
585 t_cfg->rx_linereset = in exynos_ufs_specify_phy_time_attr()
586 exynos_ufs_calc_time_cntr(ufs, attr->rx_dif_p_nsec); in exynos_ufs_specify_phy_time_attr()
587 t_cfg->rx_hibern8_wait = in exynos_ufs_specify_phy_time_attr()
588 exynos_ufs_calc_time_cntr(ufs, attr->rx_hibern8_wait_nsec); in exynos_ufs_specify_phy_time_attr()
589 t_cfg->rx_base_n_val = in exynos_ufs_specify_phy_time_attr()
590 exynos_ufs_calc_time_cntr(ufs, attr->rx_base_unit_nsec); in exynos_ufs_specify_phy_time_attr()
591 t_cfg->rx_gran_n_val = in exynos_ufs_specify_phy_time_attr()
592 exynos_ufs_calc_time_cntr(ufs, attr->rx_gran_unit_nsec); in exynos_ufs_specify_phy_time_attr()
593 t_cfg->rx_sleep_cnt = in exynos_ufs_specify_phy_time_attr()
594 exynos_ufs_calc_time_cntr(ufs, attr->rx_sleep_cnt); in exynos_ufs_specify_phy_time_attr()
595 t_cfg->rx_stall_cnt = in exynos_ufs_specify_phy_time_attr()
596 exynos_ufs_calc_time_cntr(ufs, attr->rx_stall_cnt); in exynos_ufs_specify_phy_time_attr()
601 struct ufs_hba *hba = ufs->hba; in exynos_ufs_config_phy_time_attr()
602 struct ufs_phy_time_cfg *t_cfg = &ufs->t_cfg; in exynos_ufs_config_phy_time_attr()
611 ufs->drv_data->uic_attr->rx_filler_enable); in exynos_ufs_config_phy_time_attr()
613 RX_LINERESET(t_cfg->rx_linereset)); in exynos_ufs_config_phy_time_attr()
615 RX_BASE_NVAL_L(t_cfg->rx_base_n_val)); in exynos_ufs_config_phy_time_attr()
617 RX_BASE_NVAL_H(t_cfg->rx_base_n_val)); in exynos_ufs_config_phy_time_attr()
619 RX_GRAN_NVAL_L(t_cfg->rx_gran_n_val)); in exynos_ufs_config_phy_time_attr()
621 RX_GRAN_NVAL_H(t_cfg->rx_gran_n_val)); in exynos_ufs_config_phy_time_attr()
623 RX_OV_SLEEP_CNT(t_cfg->rx_sleep_cnt)); in exynos_ufs_config_phy_time_attr()
625 RX_OV_STALL_CNT(t_cfg->rx_stall_cnt)); in exynos_ufs_config_phy_time_attr()
630 TX_LINERESET_P(t_cfg->tx_linereset_p)); in exynos_ufs_config_phy_time_attr()
632 TX_HIGH_Z_CNT_L(t_cfg->tx_high_z_cnt)); in exynos_ufs_config_phy_time_attr()
634 TX_HIGH_Z_CNT_H(t_cfg->tx_high_z_cnt)); in exynos_ufs_config_phy_time_attr()
636 TX_BASE_NVAL_L(t_cfg->tx_base_n_val)); in exynos_ufs_config_phy_time_attr()
638 TX_BASE_NVAL_H(t_cfg->tx_base_n_val)); in exynos_ufs_config_phy_time_attr()
640 TX_GRAN_NVAL_L(t_cfg->tx_gran_n_val)); in exynos_ufs_config_phy_time_attr()
642 TX_GRAN_NVAL_H(t_cfg->tx_gran_n_val)); in exynos_ufs_config_phy_time_attr()
645 TX_OV_SLEEP_CNT(t_cfg->tx_sleep_cnt)); in exynos_ufs_config_phy_time_attr()
647 ufs->drv_data->uic_attr->tx_min_activatetime); in exynos_ufs_config_phy_time_attr()
655 struct ufs_hba *hba = ufs->hba; in exynos_ufs_config_phy_cap_attr()
656 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; in exynos_ufs_config_phy_cap_attr()
664 attr->rx_hs_g1_sync_len_cap); in exynos_ufs_config_phy_cap_attr()
667 attr->rx_hs_g2_sync_len_cap); in exynos_ufs_config_phy_cap_attr()
670 attr->rx_hs_g3_sync_len_cap); in exynos_ufs_config_phy_cap_attr()
673 attr->rx_hs_g1_prep_sync_len_cap); in exynos_ufs_config_phy_cap_attr()
676 attr->rx_hs_g2_prep_sync_len_cap); in exynos_ufs_config_phy_cap_attr()
679 attr->rx_hs_g3_prep_sync_len_cap); in exynos_ufs_config_phy_cap_attr()
682 if (attr->rx_adv_fine_gran_sup_en == 0) { in exynos_ufs_config_phy_cap_attr()
687 if (attr->rx_min_actv_time_cap) in exynos_ufs_config_phy_cap_attr()
691 attr->rx_min_actv_time_cap); in exynos_ufs_config_phy_cap_attr()
693 if (attr->rx_hibern8_time_cap) in exynos_ufs_config_phy_cap_attr()
696 attr->rx_hibern8_time_cap); in exynos_ufs_config_phy_cap_attr()
698 } else if (attr->rx_adv_fine_gran_sup_en == 1) { in exynos_ufs_config_phy_cap_attr()
700 if (attr->rx_adv_fine_gran_step) in exynos_ufs_config_phy_cap_attr()
704 attr->rx_adv_fine_gran_step)); in exynos_ufs_config_phy_cap_attr()
706 if (attr->rx_adv_min_actv_time_cap) in exynos_ufs_config_phy_cap_attr()
710 attr->rx_adv_min_actv_time_cap); in exynos_ufs_config_phy_cap_attr()
712 if (attr->rx_adv_hibern8_time_cap) in exynos_ufs_config_phy_cap_attr()
716 attr->rx_adv_hibern8_time_cap); in exynos_ufs_config_phy_cap_attr()
725 struct ufs_hba *hba = ufs->hba; in exynos_ufs_establish_connt()
750 if (ufs->opts & EXYNOS_UFS_OPT_UFSPR_SECURE) in exynos_ufs_config_smu()
769 struct ufs_hba *hba = ufs->hba; in exynos_ufs_config_sync_pattern_mask()
770 u8 g = max_t(u32, pwr->gear_rx, pwr->gear_tx); in exynos_ufs_config_sync_pattern_mask()
806 major = FIELD_GET(UFS_HW_VER_MAJOR_MASK, hba->ufs_version); in exynos_ufs_get_hs_gear()
811 /* Default is HS-G3 */ in exynos_ufs_get_hs_gear()
820 struct phy *generic_phy = ufs->phy; in exynos_ufs_pre_pwr_mode()
826 ret = -EINVAL; in exynos_ufs_pre_pwr_mode()
842 if (ufs->drv_data->pre_pwr_change) in exynos_ufs_pre_pwr_mode()
843 ufs->drv_data->pre_pwr_change(ufs, dev_req_params); in exynos_ufs_pre_pwr_mode()
848 switch (dev_req_params->hs_rate) { in exynos_ufs_pre_pwr_mode()
871 struct phy *generic_phy = ufs->phy; in exynos_ufs_post_pwr_mode()
872 int gear = max_t(u32, pwr_req->gear_rx, pwr_req->gear_tx); in exynos_ufs_post_pwr_mode()
873 int lanes = max_t(u32, pwr_req->lane_rx, pwr_req->lane_tx); in exynos_ufs_post_pwr_mode()
883 if (ufs->drv_data->post_pwr_change) in exynos_ufs_post_pwr_mode()
884 ufs->drv_data->post_pwr_change(ufs, pwr_req); in exynos_ufs_post_pwr_mode()
887 switch (pwr_req->hs_rate) { in exynos_ufs_post_pwr_mode()
895 "FAST", pwr_req->hs_rate == PA_HS_MODE_A ? "A" : "B", in exynos_ufs_post_pwr_mode()
902 dev_info(hba->dev, "Power mode changed to : %s\n", pwr_str); in exynos_ufs_post_pwr_mode()
945 struct ufs_hba *hba = ufs->hba; in exynos_ufs_phy_init()
946 struct phy *generic_phy = ufs->phy; in exynos_ufs_phy_init()
949 if (ufs->avail_ln_rx == 0 || ufs->avail_ln_tx == 0) { in exynos_ufs_phy_init()
951 &ufs->avail_ln_rx); in exynos_ufs_phy_init()
953 &ufs->avail_ln_tx); in exynos_ufs_phy_init()
954 WARN(ufs->avail_ln_rx != ufs->avail_ln_tx, in exynos_ufs_phy_init()
956 ufs->avail_ln_rx, ufs->avail_ln_tx); in exynos_ufs_phy_init()
959 phy_set_bus_width(generic_phy, ufs->avail_ln_rx); in exynos_ufs_phy_init()
962 dev_err(hba->dev, "%s: phy init failed, ret = %d\n", in exynos_ufs_phy_init()
981 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; in exynos_ufs_config_unipro()
982 struct ufs_hba *hba = ufs->hba; in exynos_ufs_config_unipro()
984 if (attr->pa_dbg_clk_period_off) in exynos_ufs_config_unipro()
985 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_clk_period_off), in exynos_ufs_config_unipro()
986 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); in exynos_ufs_config_unipro()
989 ufs->drv_data->uic_attr->tx_trailingclks); in exynos_ufs_config_unipro()
991 if (attr->pa_dbg_opt_suite1_off) in exynos_ufs_config_unipro()
992 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off), in exynos_ufs_config_unipro()
993 attr->pa_dbg_opt_suite1_val); in exynos_ufs_config_unipro()
995 if (attr->pa_dbg_opt_suite2_off) in exynos_ufs_config_unipro()
996 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite2_off), in exynos_ufs_config_unipro()
997 attr->pa_dbg_opt_suite2_val); in exynos_ufs_config_unipro()
1030 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL) in exynos_ufs_setup_clocks()
1035 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL) in exynos_ufs_setup_clocks()
1055 /* m-phy */ in exynos_ufs_pre_link()
1057 if (!(ufs->opts & EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR)) { in exynos_ufs_pre_link()
1064 if (ufs->drv_data->pre_link) in exynos_ufs_pre_link()
1065 ufs->drv_data->pre_link(ufs); in exynos_ufs_pre_link()
1075 if (ufs->opts & EXYNOS_UFS_OPT_TIMER_TICK_SELECT) { in exynos_ufs_fit_aggr_timeout()
1088 struct phy *generic_phy = ufs->phy; in exynos_ufs_post_link()
1089 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; in exynos_ufs_post_link()
1097 hci_writel(ufs, (1 << hba->nutrs) - 1, HCI_UTRL_NEXUS_TYPE); in exynos_ufs_post_link()
1098 hci_writel(ufs, (1 << hba->nutmrs) - 1, HCI_UTMRL_NEXUS_TYPE); in exynos_ufs_post_link()
1101 if (ufs->opts & EXYNOS_UFS_OPT_SKIP_CONNECTION_ESTAB) in exynos_ufs_post_link()
1105 if (attr->pa_granularity) { in exynos_ufs_post_link()
1108 attr->pa_granularity); in exynos_ufs_post_link()
1111 if (attr->pa_tactivate) in exynos_ufs_post_link()
1113 attr->pa_tactivate); in exynos_ufs_post_link()
1114 if (attr->pa_hibern8time && in exynos_ufs_post_link()
1115 !(ufs->opts & EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER)) in exynos_ufs_post_link()
1117 attr->pa_hibern8time); in exynos_ufs_post_link()
1120 if (ufs->opts & EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER) { in exynos_ufs_post_link()
1121 if (!attr->pa_granularity) in exynos_ufs_post_link()
1123 &attr->pa_granularity); in exynos_ufs_post_link()
1124 if (!attr->pa_hibern8time) in exynos_ufs_post_link()
1126 &attr->pa_hibern8time); in exynos_ufs_post_link()
1132 if (attr->pa_granularity < 1 || attr->pa_granularity > 6) { in exynos_ufs_post_link()
1134 dev_warn(hba->dev, in exynos_ufs_post_link()
1137 attr->pa_granularity); in exynos_ufs_post_link()
1138 attr->pa_granularity = 6; in exynos_ufs_post_link()
1144 if (ufs->drv_data->post_link) in exynos_ufs_post_link()
1145 ufs->drv_data->post_link(ufs); in exynos_ufs_post_link()
1152 struct device_node *np = dev->of_node; in exynos_ufs_parse_dt()
1156 ufs->drv_data = device_get_match_data(dev); in exynos_ufs_parse_dt()
1158 if (ufs->drv_data && ufs->drv_data->uic_attr) { in exynos_ufs_parse_dt()
1159 attr = ufs->drv_data->uic_attr; in exynos_ufs_parse_dt()
1162 ret = -EINVAL; in exynos_ufs_parse_dt()
1166 ufs->sysreg = syscon_regmap_lookup_by_phandle(np, "samsung,sysreg"); in exynos_ufs_parse_dt()
1167 if (IS_ERR(ufs->sysreg)) in exynos_ufs_parse_dt()
1168 ufs->sysreg = NULL; in exynos_ufs_parse_dt()
1170 if (of_property_read_u32_index(np, "samsung,sysreg", 1, in exynos_ufs_parse_dt()
1171 &ufs->shareability_reg_offset)) { in exynos_ufs_parse_dt()
1172 dev_warn(dev, "can't get an offset from sysreg. Set to default value\n"); in exynos_ufs_parse_dt()
1173 ufs->shareability_reg_offset = UFS_SHAREABILITY_OFFSET; in exynos_ufs_parse_dt()
1177 ufs->pclk_avail_min = PCLK_AVAIL_MIN; in exynos_ufs_parse_dt()
1178 ufs->pclk_avail_max = PCLK_AVAIL_MAX; in exynos_ufs_parse_dt()
1180 attr->rx_adv_fine_gran_sup_en = RX_ADV_FINE_GRAN_SUP_EN; in exynos_ufs_parse_dt()
1181 attr->rx_adv_fine_gran_step = RX_ADV_FINE_GRAN_STEP_VAL; in exynos_ufs_parse_dt()
1182 attr->rx_adv_min_actv_time_cap = RX_ADV_MIN_ACTV_TIME_CAP; in exynos_ufs_parse_dt()
1183 attr->pa_granularity = PA_GRANULARITY_VAL; in exynos_ufs_parse_dt()
1184 attr->pa_tactivate = PA_TACTIVATE_VAL; in exynos_ufs_parse_dt()
1185 attr->pa_hibern8time = PA_HIBERN8TIME_VAL; in exynos_ufs_parse_dt()
1194 ufs->hba = hba; in exynos_ufs_priv_init()
1195 ufs->opts = ufs->drv_data->opts; in exynos_ufs_priv_init()
1196 ufs->rx_sel_idx = PA_MAXDATALANES; in exynos_ufs_priv_init()
1197 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX) in exynos_ufs_priv_init()
1198 ufs->rx_sel_idx = 0; in exynos_ufs_priv_init()
1199 hba->priv = (void *)ufs; in exynos_ufs_priv_init()
1200 hba->quirks = ufs->drv_data->quirks; in exynos_ufs_priv_init()
1207 * hardware on Exynos and Exynos-based SoCs. The interface to this hardware is
1222 * struct fmp_sg_entry - nonstandard format of PRDT entries when FMP is enabled
1225 * bits of the 'size' field, i.e. the last 32-bit word. When these
1230 * @file_enckey: The first half of the AES-XTS key with all bytes reserved
1231 * @file_twkey: The second half of the AES-XTS key with all bytes reserved
1259 struct blk_crypto_profile *profile = &hba->crypto_profile; in exynos_ufs_fmp_init()
1276 * downstream driver source for gs101 and other Exynos-based SoCs. It in exynos_ufs_fmp_init()
1279 * on other Exynos-based SoCs too, and might even still be the only way in exynos_ufs_fmp_init()
1284 if (!(ufs->opts & EXYNOS_UFS_OPT_UFSPR_SECURE)) in exynos_ufs_fmp_init()
1295 dev_warn(hba->dev, in exynos_ufs_fmp_init()
1308 dev_err(hba->dev, in exynos_ufs_fmp_init()
1315 err = devm_blk_crypto_profile_init(hba->dev, profile, 0); in exynos_ufs_fmp_init()
1318 dev_err(hba->dev, "Failed to initialize crypto profile: %d\n", in exynos_ufs_fmp_init()
1322 profile->max_dun_bytes_supported = AES_BLOCK_SIZE; in exynos_ufs_fmp_init()
1323 profile->dev = hba->dev; in exynos_ufs_fmp_init()
1324 profile->modes_supported[BLK_ENCRYPTION_MODE_AES_256_XTS] = in exynos_ufs_fmp_init()
1327 /* Advertise crypto support to ufshcd-core. */ in exynos_ufs_fmp_init()
1328 hba->caps |= UFSHCD_CAP_CRYPTO; in exynos_ufs_fmp_init()
1330 /* Advertise crypto quirks to ufshcd-core. */ in exynos_ufs_fmp_init()
1331 hba->quirks |= UFSHCD_QUIRK_CUSTOM_CRYPTO_PROFILE | in exynos_ufs_fmp_init()
1341 if (!(hba->caps & UFSHCD_CAP_CRYPTO)) in exynos_ufs_fmp_resume()
1347 dev_err(hba->dev, in exynos_ufs_fmp_resume()
1353 dev_err(hba->dev, in exynos_ufs_fmp_resume()
1360 key + AES_KEYSIZE_256 - (j + 1) * sizeof(u64))); in fmp_key_word()
1369 const u8 *enckey = crypt_ctx->bc_key->raw; in exynos_ufs_fmp_fill_prdt()
1371 u64 dun_lo = crypt_ctx->bc_dun[0]; in exynos_ufs_fmp_fill_prdt()
1372 u64 dun_hi = crypt_ctx->bc_dun[1]; in exynos_ufs_fmp_fill_prdt()
1376 if (WARN_ON_ONCE(!(hba->caps & UFSHCD_CAP_CRYPTO))) in exynos_ufs_fmp_fill_prdt()
1377 return -EIO; in exynos_ufs_fmp_fill_prdt()
1385 if (prd->base.size != cpu_to_le32(DATA_UNIT_SIZE - 1)) { in exynos_ufs_fmp_fill_prdt()
1386 dev_err(hba->dev, in exynos_ufs_fmp_fill_prdt()
1388 return -EIO; in exynos_ufs_fmp_fill_prdt()
1392 prd->base.size |= cpu_to_le32((FMP_ALGO_MODE_AES_XTS << 28) | in exynos_ufs_fmp_fill_prdt()
1396 prd->file_iv[0] = cpu_to_be64(dun_hi); in exynos_ufs_fmp_fill_prdt()
1397 prd->file_iv[1] = cpu_to_be64(dun_lo); in exynos_ufs_fmp_fill_prdt()
1401 prd->file_enckey[j] = fmp_key_word(enckey, j); in exynos_ufs_fmp_fill_prdt()
1402 prd->file_twkey[j] = fmp_key_word(twkey, j); in exynos_ufs_fmp_fill_prdt()
1429 struct device *dev = hba->dev; in exynos_ufs_init()
1436 return -ENOMEM; in exynos_ufs_init()
1438 /* exynos-specific hci */ in exynos_ufs_init()
1439 ufs->reg_hci = devm_platform_ioremap_resource_byname(pdev, "vs_hci"); in exynos_ufs_init()
1440 if (IS_ERR(ufs->reg_hci)) { in exynos_ufs_init()
1442 return PTR_ERR(ufs->reg_hci); in exynos_ufs_init()
1446 ufs->reg_unipro = devm_platform_ioremap_resource_byname(pdev, "unipro"); in exynos_ufs_init()
1447 if (IS_ERR(ufs->reg_unipro)) { in exynos_ufs_init()
1449 return PTR_ERR(ufs->reg_unipro); in exynos_ufs_init()
1453 ufs->reg_ufsp = devm_platform_ioremap_resource_byname(pdev, "ufsp"); in exynos_ufs_init()
1454 if (IS_ERR(ufs->reg_ufsp)) { in exynos_ufs_init()
1456 return PTR_ERR(ufs->reg_ufsp); in exynos_ufs_init()
1465 ufs->phy = devm_phy_get(dev, "ufs-phy"); in exynos_ufs_init()
1466 if (IS_ERR(ufs->phy)) { in exynos_ufs_init()
1467 ret = PTR_ERR(ufs->phy); in exynos_ufs_init()
1468 dev_err(dev, "failed to get ufs-phy\n"); in exynos_ufs_init()
1476 if (ufs->drv_data->drv_init) { in exynos_ufs_init()
1477 ret = ufs->drv_data->drv_init(ufs); in exynos_ufs_init()
1479 dev_err(dev, "failed to init drv-data\n"); in exynos_ufs_init()
1491 hba->host->dma_alignment = DATA_UNIT_SIZE - 1; in exynos_ufs_init()
1495 hba->priv = NULL; in exynos_ufs_init()
1515 dev_err(hba->dev, "timeout host sw-reset\n"); in exynos_ufs_host_reset()
1516 ret = -ETIMEDOUT; in exynos_ufs_host_reset()
1535 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; in exynos_ufs_pre_hibern8()
1538 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL) in exynos_ufs_pre_hibern8()
1542 if (ufs->opts & EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER) { in exynos_ufs_pre_hibern8()
1546 int h8_time = attr->pa_hibern8time * in exynos_ufs_pre_hibern8()
1547 granularity_tbl[attr->pa_granularity - 1]; in exynos_ufs_pre_hibern8()
1552 delta = h8_time - ktime_us_delta(ktime_get(), in exynos_ufs_pre_hibern8()
1553 ufs->entry_hibern8_t); in exynos_ufs_pre_hibern8()
1570 ufs->entry_hibern8_t = ktime_get(); in exynos_ufs_post_hibern8()
1572 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL) in exynos_ufs_post_hibern8()
1591 hba->host->max_segment_size = DATA_UNIT_SIZE; in exynos_ufs_hce_enable_notify()
1593 if (ufs->drv_data->pre_hce_enable) { in exynos_ufs_hce_enable_notify()
1594 ret = ufs->drv_data->pre_hce_enable(ufs); in exynos_ufs_hce_enable_notify()
1606 if (!(ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL)) in exynos_ufs_hce_enable_notify()
1609 if (ufs->drv_data->post_hce_enable) in exynos_ufs_hce_enable_notify()
1610 ret = ufs->drv_data->post_hce_enable(ufs); in exynos_ufs_hce_enable_notify()
1678 phy_power_off(ufs->phy); in exynos_ufs_suspend()
1688 phy_power_on(ufs->phy); in exynos_ufs_resume()
1725 return -ETIME; in exynosauto_ufs_vh_wait_ph_ready()
1730 struct device *dev = hba->dev; in exynosauto_ufs_vh_init()
1737 return -ENOMEM; in exynosauto_ufs_vh_init()
1739 /* exynos-specific hci */ in exynosauto_ufs_vh_init()
1740 ufs->reg_hci = devm_platform_ioremap_resource_byname(pdev, "vs_hci"); in exynosauto_ufs_vh_init()
1741 if (IS_ERR(ufs->reg_hci)) { in exynosauto_ufs_vh_init()
1743 return PTR_ERR(ufs->reg_hci); in exynosauto_ufs_vh_init()
1750 ufs->drv_data = device_get_match_data(dev); in exynosauto_ufs_vh_init()
1751 if (!ufs->drv_data) in exynosauto_ufs_vh_init()
1752 return -ENODEV; in exynosauto_ufs_vh_init()
1761 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; in fsd_ufs_pre_link()
1762 struct ufs_hba *hba = ufs->hba; in fsd_ufs_pre_link()
1765 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_clk_period_off), in fsd_ufs_pre_link()
1766 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); in fsd_ufs_pre_link()
1772 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); in fsd_ufs_pre_link()
1778 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); in fsd_ufs_pre_link()
1790 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off), in fsd_ufs_pre_link()
1802 struct ufs_hba *hba = ufs->hba; in fsd_ufs_post_link()
1840 struct ufs_hba *hba = ufs->hba; in fsd_ufs_pre_pwr_change()
1857 return (16 * 1000 * 1000000UL / ufs->mclk_rate); in get_mclk_period_unipro_18()
1862 struct ufs_hba *hba = ufs->hba; in gs101_ufs_pre_link()
1866 rx_line_reset_period = (RX_LINE_RESET_TIME * ufs->mclk_rate) in gs101_ufs_pre_link()
1868 tx_line_reset_period = (TX_LINE_RESET_TIME * ufs->mclk_rate) in gs101_ufs_pre_link()
1877 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); in gs101_ufs_pre_link()
1892 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); in gs101_ufs_pre_link()
1918 struct ufs_hba *hba = ufs->hba; in gs101_ufs_post_link()
1936 struct ufs_hba *hba = ufs->hba; in gs101_ufs_pre_pwr_change()
1975 struct device *dev = &pdev->dev; in exynos_ufs_probe()
1980 if (drv_data && drv_data->vops) in exynos_ufs_probe()
1981 vops = drv_data->vops; in exynos_ufs_probe()
1997 phy_power_off(ufs->phy); in exynos_ufs_remove()
1998 phy_exit(ufs->phy); in exynos_ufs_remove()
2145 { .compatible = "google,gs101-ufs",
2147 { .compatible = "samsung,exynos7-ufs",
2149 { .compatible = "samsung,exynosautov9-ufs",
2151 { .compatible = "samsung,exynosautov9-ufs-vh",
2153 { .compatible = "tesla,fsd-ufs",
2170 .name = "exynos-ufshc",