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/linux/tools/perf/pmu-events/arch/x86/rocketlake/
H A D	frontend.json	3 "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.", 7 "PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.", 16 "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byt [all...]
/linux/tools/perf/pmu-events/arch/x86/icelakex/
H A D	frontend.json	3 "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.", 7 "PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.", 16 "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byt [all...]
/linux/tools/perf/pmu-events/arch/x86/tigerlake/
H A D	frontend.json	3 "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.", 7 "PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.", 16 "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byt [all...]
/linux/tools/perf/pmu-events/arch/x86/icelake/
H A D	frontend.json	3 "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.", 7 "PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.", 16 "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byt [all...]
/linux/tools/perf/pmu-events/arch/x86/emeraldrapids/
H A D	frontend.json	7 …"PublicDescription": "Number of times the front-end is resteered when it finds a branch instructio… 16 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length … 29 "BriefDescription": "DSB-to-MITE switch true penalty cycles.", 33 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou… 44 …ions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Availabl… 55 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th… 93 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", 99 …ter an interval where the front-end delivered no uops for a period of at least 1 cycle which was n… 104 … after an interval where the front-end delivered no uops for a period of 128 cycles which was not … 110 … after an interval where the front-end delivered no uops for a period of 128 cycles which was not … [all …]
/linux/tools/perf/pmu-events/arch/x86/sapphirerapids/
H A D	frontend.json	7 …"PublicDescription": "Number of times the front-end is resteered when it finds a branch instructio… 16 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length … 29 "BriefDescription": "DSB-to-MITE switch true penalty cycles.", 33 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou… 44 …ions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Availabl… 55 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th… 93 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", 99 …ter an interval where the front-end delivered no uops for a period of at least 1 cycle which was n… 104 … after an interval where the front-end delivered no uops for a period of 128 cycles which was not … 110 … after an interval where the front-end delivered no uops for a period of 128 cycles which was not … [all …]
/linux/tools/perf/pmu-events/arch/x86/graniterapids/
H A D	frontend.json	7 …"PublicDescription": "Number of times the front-end is resteered when it finds a branch instructio… 16 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length … 29 "BriefDescription": "DSB-to-MITE switch true penalty cycles.", 33 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou… 55 …ions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Availabl… 69 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th… 116 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", 122 …ter an interval where the front-end delivered no uops for a period of at least 1 cycle which was n… 127 … after an interval where the front-end delivered no uops for a period of 128 cycles which was not … 133 … after an interval where the front-end delivered no uops for a period of 128 cycles which was not … [all …]
/linux/tools/perf/pmu-events/arch/x86/alderlake/
H A D	frontend.json	17 …"PublicDescription": "Number of times the front-end is resteered when it finds a branch instructio… 27 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length … 42 "BriefDescription": "DSB-to-MITE switch true penalty cycles.", 46 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou… 58 …ions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Availabl… 70 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th… 112 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", 118 …ter an interval where the front-end delivered no uops for a period of at least 1 cycle which was n… 124 … after an interval where the front-end delivered no uops for a period of 128 cycles which was not … 130 … after an interval where the front-end delivered no uops for a period of 128 cycles which was not … [all …]
/linux/tools/perf/pmu-events/arch/x86/skylake/
H A D	frontend.json	3 …front end is resteered, mainly when the BPU cannot provide a correct prediction and this is correc… 7 …"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch… 16 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length … 21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", 25 …e Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Strea… 30 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 34 …-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of th… 46 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", 58 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th… 97 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", [all …]
/linux/tools/perf/pmu-events/arch/x86/cascadelakex/
H A D	frontend.json	3 …front end is resteered, mainly when the BPU cannot provide a correct prediction and this is correc… 7 …"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch… 16 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length … 21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", 25 …e Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Strea… 30 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 34 …-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of th… 46 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", 58 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th… 97 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", [all …]
/linux/tools/perf/pmu-events/arch/x86/skylakex/
H A D	frontend.json	3 …front end is resteered, mainly when the BPU cannot provide a correct prediction and this is correc… 7 …"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch… 16 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length … 21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", 25 …e Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Strea… 30 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 34 …-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of th… 46 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", 58 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th… 97 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", [all …]
/linux/tools/perf/pmu-events/arch/x86/meteorlake/
H A D	frontend.json	17 …"PublicDescription": "Number of times the front-end is resteered when it finds a branch instructio… 27 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length … 42 "BriefDescription": "DSB-to-MITE switch true penalty cycles.", 46 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou… 78 …ions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Availabl… 127 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th… 187 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", 193 …ter an interval where the front-end delivered no uops for a period of at least 1 cycle which was n… 199 … after an interval where the front-end delivered no uops for a period of 128 cycles which was not … 205 … after an interval where the front-end delivered no uops for a period of 128 cycles which was not … [all …]
/linux/tools/perf/pmu-events/arch/x86/pantherlake/
H A D	frontend.json	17 …"PublicDescription": "Number of times the front-end is resteered when it finds a branch instructio… 63 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length … 78 "BriefDescription": "DSB-to-MITE switch true penalty cycles.", 82 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou… 106 …ions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Availabl… 118 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th… 170 … after an interval where the front-end delivered no uops for a period of 128 cycles which was not … 176 … after an interval where the front-end delivered no uops for a period of 128 cycles which was not … 182 …d after an interval where the front-end delivered no uops for a period of 16 cycles which was not … 188 …ons that are delivered to the back-end after a front-end stall of at least 16 cycles. During this … [all …]
/linux/tools/perf/pmu-events/arch/x86/silvermont/
H A D	frontend.json	7 …front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction… 16 …front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction… 25 …front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction… 66 …s entered into a ucode flow in the FEC. Includes inserted flows due to front-end detected faults … 70 …e most common case that this counts is when a micro-coded instruction is encountered by the front …
H A D	pipeline.json	107 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp… 116 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp… 126 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp… 136 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp… 146 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp… 156 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp… 206 … For instructions that consist of multiple micro-ops, this event counts exactly once, as the last … 215 … For instructions that consist of multiple micro-ops, this event counts the retirement of the last… 223 …front end of the machine is notified that it must restart, so no more instructions will be decoded… 228 "BriefDescription": "Self-Modifying Code detected", [all …]
/linux/tools/perf/pmu-events/arch/x86/lunarlake/
H A D	frontend.json	17 …"PublicDescription": "Number of times the front-end is resteered when it finds a branch instructio… 63 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length … 87 "BriefDescription": "DSB-to-MITE switch true penalty cycles.", 91 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou… 123 …ions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Availabl… 172 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th… 232 … after an interval where the front-end delivered no uops for a period of 128 cycles which was not … 238 … after an interval where the front-end delivered no uops for a period of 128 cycles which was not … 244 …d after an interval where the front-end delivered no uops for a period of 16 cycles which was not … 250 …ons that are delivered to the back-end after a front-end stall of at least 16 cycles. During this … [all …]
/linux/Documentation/admin-guide/
H A D	pstore-blk.rst	1 .. SPDX-License-Identifier: GPL-2.0 7 ------------ 10 block device and non-block device before the system crashes. You can get 13 mount -t pstore pstore /sys/fs/pstore 17 --------------------- 27 Configurations for driver are all about block device and non-block device, 31 ----------------------- 51 #. /dev/<disk_name><decimal> represents the device number of partition - device 53 #. /dev/<disk_name>p<decimal> - same as the above; this form is used when disk 60 #. PARTUUID=00112233-4455-6677-8899-AABBCCDDEEFF represents the unique id of [all …]
/linux/tools/perf/pmu-events/arch/x86/arrowlake/
H A D	frontend.json	17 …"PublicDescription": "Number of times the front-end is resteered when it finds a branch instructio… 37 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length … 52 "BriefDescription": "DSB-to-MITE switch true penalty cycles.", 56 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou… 96 …ions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Availabl… 182 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th… 260 … after an interval where the front-end delivered no uops for a period of 128 cycles which was not … 266 … after an interval where the front-end delivered no uops for a period of 128 cycles which was not … 272 …d after an interval where the front-end delivered no uops for a period of 16 cycles which was not … 278 …ons that are delivered to the back-end after a front-end stall of at least 16 cycles. During this … [all …]
/linux/tools/perf/pmu-events/arch/x86/goldmontplus/
H A D	pipeline.json	229 "BriefDescription": "Instructions retired - using Reduced Skid PEBS feature", 250 …ocation is stalled waiting for a mispredicted jump to retire or other branch-like conditions (e.g.… 259 …ource in the backend. Including but not limited to resources such as the Re-order Buffer (ROB), r… 335 …r of times that the machines clears due to a page fault. Covers both I-side and D-side(Loads/Store… 340 "BriefDescription": "Self-Modifying Code detected", 344 …ction and has to perform a machine clear because of that modification. Self-modifying code (SMC) … 349 "BriefDescription": "Uops issued to the back end per cycle", 353 …front end and allocated into the back end of the machine. This event counts uops that retire as w… 357 "BriefDescription": "Uops requested but not-delivered to the back-end per cycle", 361 …front-end inefficiencies. I.e. when front-end of the machine is not delivering uops to the back-en… [all …]
/linux/tools/perf/pmu-events/arch/x86/goldmont/
H A D	pipeline.json	240 …ocation is stalled waiting for a mispredicted jump to retire or other branch-like conditions (e.g.… 249 …ource in the backend. Including but not limited to resources such as the Re-order Buffer (ROB), r… 321 "BriefDescription": "Self-Modifying Code detected", 325 …ction and has to perform a machine clear because of that modification. Self-modifying code (SMC) … 330 "BriefDescription": "Uops issued to the back end per cycle", 334 …front end and allocated into the back end of the machine. This event counts uops that retire as w… 338 "BriefDescription": "Uops requested but not-delivered to the back-end per cycle", 342 …front-end inefficiencies. I.e. when front-end of the machine is not delivering uops to the back-en… 370 …ued by the micro-sequencer (MS). Counts both the uops from a micro-coded instruction, and the uop…
/linux/include/media/
H A D	demux.h	4 * The Kernel Digital TV Demux kABI defines a driver-internal interface for 5 * registering low-level, hardware specific driver to a hardware independent 64 * enum ts_filter_type - filter type bitmap for dmx_ts_feed.set\(\) 69 * @TS_DECODER: Send stream to built-in decoder (if present). 81 * struct dmx_ts_feed - Structure that contains a TS feed filter 83 * @is_filtering: Set to non-zero when filtering in progress 112 * struct dmx_section_filter - Structure that describes a section filter 120 * @parent: Back-pointer to struct dmx_section_feed. 139 * struct dmx_section_feed - Structure that contains a section feed filter 141 * @is_filtering: Set to non-zero when filtering in progress [all …]
/linux/tools/perf/pmu-events/arch/x86/haswellx/
H A D	frontend.json	3 …front end is resteered, mainly when the BPU cannot provide a correct prediction and this is correc… 7 "PublicDescription": "Number of front end re-steers due to BPU misprediction.", 12 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 28 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.", 36 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.", 153 …s event counts cycles during which the microcode sequencer assisted the Front-end in delivering uo… 209 …"PublicDescription": "This event counts uops delivered by the Front-end with the assistance of the… 219 …Front-end to the Resource Allocation Table (RAT) while the Back-end of the processor is not stalle… 230 …Front-end allocated exactly zero uops to the Resource Allocation Table (RAT) while the Back-end of… 256 "BriefDescription": "Cycles with less than 2 uops delivered by the front end.", [all …]
/linux/tools/perf/pmu-events/arch/x86/haswell/
H A D	frontend.json	3 …front end is resteered, mainly when the BPU cannot provide a correct prediction and this is correc… 7 "PublicDescription": "Number of front end re-steers due to BPU misprediction.", 12 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 28 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.", 36 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.", 153 …s event counts cycles during which the microcode sequencer assisted the Front-end in delivering uo… 209 …"PublicDescription": "This event counts uops delivered by the Front-end with the assistance of the… 219 …Front-end to the Resource Allocation Table (RAT) while the Back-end of the processor is not stalle… 230 …Front-end allocated exactly zero uops to the Resource Allocation Table (RAT) while the Back-end of… 256 "BriefDescription": "Cycles with less than 2 uops delivered by the front end.", [all …]
/linux/tools/perf/pmu-events/arch/x86/sandybridge/
H A D	frontend.json	3 …front end is resteered, mainly when the BPU cannot provide a correct prediction and this is correc… 11 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches.", 19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 23 …-end cannot accept new micro-ops. The penalty for these switches is potentially several cycles o… 160 …front-end in delivering uops. Microcode assists are used for complex instructions or scenarios th… 222 …-end per cycle, per thread, when the back-end was not stalled. In the ideal case 4 uops can be de… 246 "BriefDescription": "Cycles when 1 or more uops were delivered to the by the front end.", 265 "BriefDescription": "Cycles with less than 2 uops delivered by the front end.", 274 "BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
/linux/tools/perf/pmu-events/arch/x86/jaketown/
H A D	frontend.json	3 …front end is resteered, mainly when the BPU cannot provide a correct prediction and this is correc… 11 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches.", 19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 23 …-end cannot accept new micro-ops. The penalty for these switches is potentially several cycles o… 160 …front-end in delivering uops. Microcode assists are used for complex instructions or scenarios th… 222 …-end per cycle, per thread, when the back-end was not stalled. In the ideal case 4 uops can be de… 246 "BriefDescription": "Cycles when 1 or more uops were delivered to the by the front end.", 265 "BriefDescription": "Cycles with less than 2 uops delivered by the front end.", 274 "BriefDescription": "Cycles with less than 3 uops delivered by the front end.",

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