freeze\-bridge\-controller (full) in projects: linux

Project(s)

Full Search
Definition
Symbol
File Path
History
Type

Searched +full:freeze +full:- +full:bridge +full:- +full:controller (Results 1 – 20 of 20) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/fpga/
H A D	altera-freeze-bridge.txt	1 Altera Freeze Bridge Controller Driver 3 The Altera Freeze Bridge Controller manages one or more freeze bridges. 4 The controller can freeze/disable the bridges which prevents signal 5 changes from passing through the bridge. The controller can also 7 bridge normally. 10 - compatible : Should contain "altr,freeze-bridge-controller" 11 - regs : base address and size for freeze bridge module 13 See Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings. 16 freeze-controller@100000450 { 17 compatible = "altr,freeze-bridge-controller"; [all …]
H A D	fpga-region.txt	`6 - Introduction 7 - Terminology 8 - Sequence 9 - FPGA Region 10 - Supported Use Models 11 - Device Tree Examples 12 - Constraints 57 FPGA Bridge 64 * During Partial Reconfiguration of a specific region, that region's bridge 70 own bridge an [all...]`
H A D	fpga-region.yaml	`1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/fpga/fpga-region.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Michal Simek <michal.simek@amd.com> 14 - Introduction 15 - Terminology 16 - Sequence 17 - FPGA Region 18 - Supported Use Models [all …]`
/freebsd/sys/powerpc/powermac/
H A D	macio.c	`1 /- 2 SPDX-License-Identifier: BSD-3-Clause 31 * Driver for KeyLargo/Pangea, the MacPPC south bridge ASIC. 158 { 0x0017106b, "Paddington I/O Controller" }, 159 { 0x0022106b, "KeyLargo I/O Controller" }, 160 { 0x0025106b, "Pangea I/O Controller" }, 161 { 0x003e106b, "Intrepid I/O Controller" }, 162 { 0x0041106b, "K2 KeyLargo I/O Controller" }, 163 { 0x004f106b, "Shasta I/O Controller" }, 181 { "escc-legacy", MACIO_QUIRK_IGNORE }, [all …]`
/freebsd/sys/conf/
H A D	NOTES	2 # NOTES -- Lines that can be cut/pasted into kernel and hints configs. 11 # Please use ``make LINT'' to create an old-style LINT file if you want to 12 # do kernel test-builds. 48 # auto-size based on physical memory. 66 # after most other flags. Here we use it to inhibit use of non-optimal 67 # gcc built-in functions (e.g., memcmp). 70 # The following is equivalent to 'config -g KERNELNAME' and creates 71 # 'kernel.debug' compiled with -g debugging as well as a normal 81 makeoptions CONF_CFLAGS=-fno-builtin #Don't allow use of memcmp, etc. 82 #makeoptions DEBUG=-g #Build kernel with gdb(1) debug symbols [all …]
/freebsd/sys/dev/nvme/
H A D	nvme_ctrlr.c	1 /- 2 SPDX-License-Identifier: BSD-2-Clause 4 * Copyright (C) 2012-2016 Intel Corporation 52 #define B4_CHK_RDY_DELAY_MS 2300 /* work around controller bug */ 60 bus_barrier(ctrlr->resource, 0, rman_get_size(ctrlr->resource), flags); in nvme_ctrlr_barrier() 72 sbuf_printf(&sb, "name=\"%s\" ", device_get_nameunit(ctrlr->dev)); in nvme_ctrlr_devctl_va() 76 devctl_notify("nvme", "controller", type, sbuf_data(&sb)); in nvme_ctrlr_devctl_va() 99 sbuf_printf(&sb, "%s: ", device_get_nameunit(ctrlr->dev)); in nvme_ctrlr_devctl_log() 119 qpair = &ctrlr->adminq; in nvme_ctrlr_construct_admin_qpair() 120 qpair->id = 0; in nvme_ctrlr_construct_admin_qpair() [all …]
/freebsd/sys/cam/
H A D	cam_ccb.h	`1 /- 4 SPDX-License-Identifier: BSD-2-Clause 89 CAM_DEV_QFREEZE = 0x00000800,/* Freeze DEV Q on execution / 129 / Non-immediate function code / 135 / Common function commands: 0x00->0x0F / 168 / SCSI Control Functions: 0x10->0x1F / 227 / HBA engine commands 0x20->0x2F / 233 / Target mode commands: 0x30->0x3F / 256 / Vendor Unique codes: 0x80->0x8F */ 269 (((ccb)->ccb_h.func_code & XPT_FC_DEV_QUEUED) == XPT_FC_DEV_QUEUED) [all …]`
/freebsd/
H A D	UPDATING	1 Updating Information for users of FreeBSD-CURRENT. 9 https://docs.freebsd.org/en/books/handbook/cutting-edge/#makeworld 22 includes various WITNESS- related kernel options, INVARIANTS, malloc 28 at runtime, run "ln -s 'abort:false,junk:false' /etc/malloc.conf".) 47 The "FreeBSD-unbound" package is renamed to "FreeBSD-local-unbound". 48 If you have set-optional or set-base installed, the new package will 61 Audio-related utilities including mixer(8) and virtual_oss(8) have 62 moved to the new FreeBSD-sound package. If you have set-optional or 63 set-base installed this package will be installed automatically, 67 Both drm-kmod and nividia-drm ports had to be updated to either no [all …]
/freebsd/share/dict/
H A D	web2a	`12 A-b-c book 13 A-b-c method 14 abdomino-uterotomy 15 Abdul-baha 16 a-be 20 able-bodied 21 able-bodiedness 22 able-minded 23 able-mindedness 27 Abor-miri [all …]`
H A D	web2	`26258 bridge 42338 controller 73447 freeze 99810 Jean-Christophe 99811 Jean-Pierre`
/freebsd/sys/arm/mv/
H A D	mv_common.c	1 /- 2 SPDX-License-Identifier: BSD-3-Clause 4 * Copyright (C) 2008-2011 MARVELL INTERNATIONAL LTD. 179 { "marvell,armada-370-neta", &decode_win_neta_setup, 181 { "mrvl,usb-ehci", &decode_win_usb_setup, &decode_win_usb_dump, &decode_win_usb_valid}, 182 { "marvell,orion-ehci", &decode_win_usb_setup, &decode_win_usb_dump, &decode_win_usb_valid }, 183 { "marvell,armada-380-xhci", &decode_win_usb3_setup, 185 { "marvell,armada-380-ahci", &decode_win_ahci_setup, 187 { "marvell,armada-380-sdhci", &decode_win_sdhci_setup, 191 { "marvell,armada-38x-crypto", &decode_win_a38x_cesa_setup, [all …]
/freebsd/sys/dev/bce/
H A D	if_bce.c	`1 /- 2 SPDX-License-Identifier: BSD-2-Clause 4 * Copyright (c) 2006-2014 QLogic Corporation 42 * BCM5706C A0, A1 (pre-production) 43 * BCM5706S A0, A1 (pre-production) 44 * BCM5708C A0, B0 (pre-production) 45 * BCM5708S A0, B0 (pre-production) 46 * BCM5709C A0 B0, B1, B2 (pre-production) 47 * BCM5709S A0, B0, B1, B2 (pre-production) 153 "QLogic NetXtreme II BCM5706 1000Base-T" }, [all …]`
/freebsd/sys/dev/qlnx/qlnxe/
H A D	reg_addr.h	2 * Copyright (c) 2017-2018 Cavium, Inc. 78 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl… 79 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea… 80 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn… 81 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea… 88 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 90 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 116 … (0x1<<9) // Fast back-to-back transaction ena… 128 … (0x1<<23) // Fast back-to-back capable. Not ap… 145 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… [all …]
/illumos-gate/usr/src/uts/common/io/qede/579xx/hsi/hw/
H A D	reg_addr_ah_compile15.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 85 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 87 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 96 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 98 … has_mem_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 144 …_SYS_ERR (0x1<<30) // Fatal or Non-Fatal Error Message s… 148 …:0x20 This is the PCIE compliant status/command register (bits 31-16: status, bits 15-0: command)… 149 …:0x20 This is the PCIE compliant status/command register (bits 31-16: status, bits 15-0: command)… [all …]
H A D	reg_addr_bb.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 84 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl… 85 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea… 86 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn… 87 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea… 89 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 91 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 99 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… [all …]
H A D	reg_addr_k2.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 84 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl… 85 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea… 86 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn… 87 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea… 89 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 91 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 99 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… [all …]
H A D	reg_addr_e5.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 84 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl… 85 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea… 86 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn… 87 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea… 89 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 91 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 99 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… [all …]
H A D	reg_addr.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 85 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl… 86 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea… 87 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn… 88 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea… 90 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 92 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 100 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… [all …]
/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A D	AttrDocs.td	1 //==--- AttrDocs.td - Attribute documentation ----------------------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===---------------------------------------------------------------------===// 9 // To test that the documentation builds cleanly, you must run clang-tblgen to 15 // To run clang-tblgen to generate the .rst file: 16 // clang-tblgen -gen-attr-docs -I <root>/llvm/tools/clang/include 17 // <root>/llvm/tools/clang/include/clang/Basic/Attr.td -o 20 // To run sphinx to generate the .html files (note that sphinx-build must be 24 // Non-Windows (from within the clang\docs directory): 25 // sphinx-build -b html _build/html [all …]
/illumos-gate/usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/
H A D	57712_reg.h	3 …//ACCESS:RW DataWidth:0x2 Description: Defines the number of sets - 3 - 256 ;2- 128; 1- 64; 0- 32 9 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… 10 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… 11 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… 12 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… 13 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… 14 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… 15 …set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… 16 …set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… 17 …set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… [all …]