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Searched +full:fpga +full:- +full:passive +full:- +full:serial (Results 1 – 10 of 10) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/fpga/
H A Daltera-passive-serial.txt1 Altera Passive Serial SPI FPGA Manager
4 referred to as "passive serial".
5 The passive serial link is not technically SPI, and might require extra
11 - compatible: Must be one of the following:
12 "altr,fpga-passive-serial",
13 "altr,fpga-arria10-passive-serial"
14 - reg: SPI chip select of the FPGA
15 - nconfig-gpios: config pin (referred to as nCONFIG in the manual)
16 - nstat-gpios: status pin (referred to as nSTATUS in the manual)
19 - confd-gpios: confd pin (referred to as CONF_DONE in the manual)
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H A Daltr,fpga-passive-serial.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/altr,fpga-passive-serial.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Altera Passive Serial SPI FPGA Manager
10 - Fabio Estevam <festevam@denx.de>
14 referred to as "passive serial".
15 The passive serial link is not technically SPI, and might require extra
21 - $ref: /schemas/spi/spi-peripheral-props.yaml#
26 - altr,fpga-passive-serial
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/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6q-lxr.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 /dts-v1/;
6 #include "imx6q-phytec-pfla02.dtsi"
9 model = "COMVETIA QSoIP LXR-2";
10 compatible = "comvetia,imx6q-lxr", "phytec,imx6q-pfla02", "fsl,imx6q";
13 stdout-path = &uart4;
17 compatible = "spi-gpio";
18 pinctrl-names = "default";
19 pinctrl-0 = <&pinctrl_spi_gpio>;
20 sck-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
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H A Dimx6q-evi.dts4 * This file is dual-licensed: you can use it either under the terms
44 /dts-v1/;
46 #include <dt-bindings/gpio/gpio.h>
47 #include <dt-bindings/interrupt-controller/irq.h>
51 compatible = "uniwest,imx6q-evi", "fsl,imx6q";
58 reg_usbh1_vbus: regulator-usbhubreset {
59 compatible = "regulator-fixed";
60 regulator-name = "usbh1_vbus";
61 regulator-min-microvolt = <5000000>;
62 regulator-max-microvolt = <5000000>;
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/freebsd/sys/contrib/device-tree/src/arm64/xilinx/
H A Dzynqmp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2014 - 2021, Xilinx, Inc.
15 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/interrupt-controller/irq.h>
19 #include <dt-bindings/power/xlnx-zynqmp-power.h>
20 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
21 #include <dt-bindings/thermal/thermal.h>
25 #address-cells = <2>;
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/freebsd/share/misc/
H A Dpci_vendors5 # Date: 2025-10-18 03:15:01
8 # the PCI ID Project at https://pci-ids.ucw.cz/.
14 # (version 2 or higher) or the 3-clause BSD License.
25 # device device_name <-- single tab
26 # subvendor subdevice subsystem_name <-- two tabs
30 # This is a relabelled RTL-8139
31 8139 AT-2500TX V3 Ethernet
41 7a09 PCI-to-PCI Bridge
51 7a19 PCI-to-PCI Bridge
57 7a29 PCI-to-PCI Bridge
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H A Dusb_vendors6 # http://www.linux-usb.org/usb-ids.html
7 # or send entries as patches (diff -u old new) in the
10 # http://www.linux-usb.org/usb.ids
13 # Date: 2025-09-15 20:34:02
20 # device device_name <-- single tab
21 # interface interface_name <-- two tabs
38 5301 GW-US54ZGL 802.11bg
54 145f NW-3100 802.11b/g 54Mbps Wireless Network Adapter [zd1211]
64 0200 TP-Link
86 120e ASI120MC-S Planetary Camera
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/freebsd/sys/dev/qlnx/qlnxe/
H A Dreg_addr.h2 * Copyright (c) 2017-2018 Cavium, Inc.
78 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl…
79 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea…
80 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn…
81 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea…
88 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of …
90 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
116 … (0x1<<9) // Fast back-to-back transaction ena…
128 … (0x1<<23) // Fast back-to-back capable. Not ap…
145 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
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/freebsd/sys/dev/cxgbe/
H A Dt4_main.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
306 * Each tunable is set to a default value here if it's known at compile-time.
307 * Otherwise it is set to -n as an indication to tweak_tunables() that it should
324 int t4_ntxq = -NTXQ;
330 int t4_nrxq = -NRXQ;
336 static int t4_ntxq_vi = -NTXQ_VI;
341 static int t4_nrxq_vi = -NRXQ_VI;
347 0, "Reserve TX queue 0 of each VI for non-flowid packets");
351 static int t4_nofldtxq = -NOFLDTXQ;
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/freebsd/sys/dev/bxe/
H A Dbxe_elink.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2007-2017 QLogic Corporation. All rights reserved.
508 /* When this pin is active high during reset, 10GBASE-T core is power
509 * down, When it is active low the 10GBASE-T is power up
774 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1)
936 (_phy)->def_md_devad, \
942 (_phy)->def_md_devad, \
970 * elink_check_lfa - This function checks if link reinitialization is required,
982 struct bxe_softc *sc = params->sc; in elink_check_lfa()
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