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/linux/Documentation/devicetree/bindings/fpga/
H A Dfpga-region.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/fpga/fpga-region.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: FPGA Region
10 - Michal Simek <michal.simek@amd.com>
14 - Introduction
15 - Terminology
16 - Sequence
17 - FPGA Region
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H A Dxlnx,pr-decoupler.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/xlnx,pr-decoupler.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nava kishore Manne <nava.kishore.manne@amd.com>
13 - $ref: fpga-bridge.yaml#
17 decouplers/fpga bridges. The controller can decouple/disable the bridges
19 can also couple / enable the bridges which allows traffic to pass through the
22 is compatible with the Xilinx LogiCORE pr-decoupler. The Dynamic Function
24 bridge. The controller safely handles AXI4MM and AXI4-Lite interfaces on a
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H A Daltr,freeze-bridge-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/altr,freeze-bridge-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The Altera Freeze Bridge Controller manages one or more freeze bridges.
11 The controller can freeze/disable the bridges which prevents signal
13 unfreeze/enable the bridges which allows traffic to pass through the bridge
17 - Xu Yilun <yilun.xu@intel.com>
20 - $ref: fpga-bridge.yaml#
24 const: altr,freeze-bridge-controller
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/linux/Documentation/driver-api/fpga/
H A Dfpga-programming.rst1 In-kernel API for FPGA Programming
5 --------
7 The in-kernel API for FPGA programming is a combination of APIs from
8 FPGA manager, bridge, and regions. The actual function used to
9 trigger FPGA programming is fpga_region_program_fpga().
12 the FPGA manager and bridges. It will:
15 * lock the mutex of the region's FPGA manager
16 * build a list of FPGA bridges if a method has been specified to do so
17 * disable the bridges
18 * program the FPGA using info passed in :c:expr:`fpga_region->info`.
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H A Dintro.rst4 The FPGA subsystem supports reprogramming FPGAs dynamically under
5 Linux. Some of the core intentions of the FPGA subsystems are:
7 * The FPGA subsystem is vendor agnostic.
9 * The FPGA subsystem separates upper layers (userspace interfaces and
11 FPGA.
16 other users. Write the linux-fpga mailing list and maintainers and
23 FPGA Manager
24 ------------
26 If you are adding a new FPGA or a new method of programming an FPGA,
27 this is the subsystem for you. Low level FPGA manager drivers contain
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/linux/drivers/fpga/tests/
H A Dfpga-region-test.c1 // SPDX-License-Identifier: GPL-2.0
3 * KUnit test for the FPGA Region
12 #include <linux/fpga/fpga-bridge.h>
13 #include <linux/fpga/fpga-mgr.h>
14 #include <linux/fpga/fpga-region.h>
53 struct mgr_stats *stats = mgr->priv; in op_write()
55 stats->write_count++; in op_write()
61 * Fake FPGA manager that implements only the write op to count the number
72 struct bridge_stats *stats = bridge->priv; in op_enable_set()
74 if (!stats->enable && enable) in op_enable_set()
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H A Dfpga-bridge-test.c1 // SPDX-License-Identifier: GPL-2.0
3 * KUnit test for the FPGA Bridge
12 #include <linux/fpga/fpga-bridge.h>
35 struct bridge_stats *stats = bridge->priv; in op_enable_set()
37 stats->enable = enable; in op_enable_set()
43 * Fake FPGA bridge that implements only the enable_set op to track
51 * register_test_bridge() - Register a fake FPGA bridge for testing.
55 * Return: Context of the newly registered FPGA bridge.
65 ctx->dev = kunit_device_register(test, dev_name); in register_test_bridge()
66 KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx->dev); in register_test_bridge()
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/linux/Documentation/fpga/
H A Ddfl.rst2 FPGA Device Feature List (DFL) Framework Overview
7 - Enno Luebbers <enno.luebbers@intel.com>
8 - Xiao Guangrong <guangrong.xiao@linux.intel.com>
9 - Wu Hao <hao.wu@intel.com>
10 - Xu Yilun <yilun.xu@intel.com>
12 The Device Feature List (DFL) FPGA framework (and drivers according to
15 configure, enumerate, open and access FPGA accelerators on platforms which
17 enables system level management functions such as FPGA reconfiguration.
24 walk through these predefined data structures to enumerate FPGA features:
25 FPGA Interface Unit (FIU), Accelerated Function Unit (AFU) and Private Features,
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/linux/drivers/pci/hotplug/
H A Dpci_hotplug_core.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2001-2002 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001-2002 IBM Corp.
13 * Greg Kroah-Hartman <greg@kroah.com>
43 const struct hotplug_slot_ops *ops = slot->ops; \
45 if (ops->get_##name) \
46 retval = ops->get_##name(slot, value); \
60 retval = get_power_status(pci_slot->hotplug, &value); in GET_STATUS()
70 struct hotplug_slot *slot = pci_slot->hotplug; in power_write_file()
81 if (slot->ops->disable_slot) in power_write_file()
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/linux/drivers/media/pci/ddbridge/
H A Dddbridge-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * ddbridge-core.c: Digital Devices bridge core functions
5 * Copyright (C) 2010-2017 Digital Devices GmbH
25 #include "ddbridge-i2c.h"
26 #include "ddbridge-regs.h"
27 #include "ddbridge-max.h"
28 #include "ddbridge-ci.h"
29 #include "ddbridge-io.h"
44 #include "ddbridge-dummy-fe.h"
57 "0-one adapter per io, 1-one per tab with io, 2-one per tab, 3-one for all");
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/linux/
H A DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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