| /linux/Documentation/devicetree/bindings/fpga/ |
| H A D | fpga-region.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/fpga/fpga-region.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: FPGA Region
10 - Michal Simek <michal.simek@amd.com>
14 - Introduction
15 - Terminology
16 - Sequence
17 - FPGA Region
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| H A D | fpga-bridge.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/fpga-bridge.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: FPGA Bridge
10 - Michal Simek <michal.simek@amd.com>
14 pattern: "^fpga-bridge(@.*|-([0-9]|[1-9][0-9]+))?$"
16 bridge-enable:
18 0 if driver should disable bridge at startup
19 1 if driver should enable bridge at startup
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| H A D | xlnx,pr-decoupler.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/xlnx,pr-decoupler.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nava kishore Manne <nava.kishore.manne@amd.com>
13 - $ref: fpga-bridge.yaml#
17 decouplers/fpga bridges. The controller can decouple/disable the bridges
18 which prevents signal changes from passing through the bridge. The controller
20 bridge normally.
22 is compatible with the Xilinx LogiCORE pr-decoupler. The Dynamic Function
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| H A D | altr,socfpga-hps2fpga-bridge.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/altr,socfpga-hps2fpga-bridge.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Altera FPGA/HPS Bridge
10 - Xu Yilun <yilun.xu@intel.com>
13 - $ref: fpga-bridge.yaml#
18 - altr,socfpga-lwhps2fpga-bridge
19 - altr,socfpga-hps2fpga-bridge
20 - altr,socfpga-fpga2hps-bridge
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| H A D | altr,socfpga-fpga2sdram-bridge.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/altr,socfpga-fpga2sdram-bridge.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Altera FPGA To SDRAM Bridge
10 - Xu Yilun <yilun.xu@intel.com>
13 - $ref: fpga-bridge.yaml#
17 const: altr,socfpga-fpga2sdram-bridge
23 - compatible
28 - |
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| H A D | altr,freeze-bridge-controller.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/altr,freeze-bridge-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Altera Freeze Bridge Controller
10 The Altera Freeze Bridge Controller manages one or more freeze bridges.
12 changes from passing through the bridge. The controller can also
13 unfreeze/enable the bridges which allows traffic to pass through the bridge
17 - Xu Yilun <yilun.xu@intel.com>
20 - $ref: fpga-bridge.yaml#
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| /linux/drivers/fpga/tests/ |
| H A D | fpga-region-test.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * KUnit test for the FPGA Region
12 #include <linux/fpga/fpga-bridge.h>
13 #include <linux/fpga/fpga-mgr.h>
14 #include <linux/fpga/fpga-region.h>
30 struct fpga_bridge *bridge; member
53 struct mgr_stats *stats = mgr->priv; in op_write()
55 stats->write_count++; in op_write()
61 * Fake FPGA manager that implements only the write op to count the number
70 static int op_enable_set(struct fpga_bridge *bridge, bool enable) in op_enable_set() argument
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| H A D | fpga-bridge-test.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * KUnit test for the FPGA Bridge
12 #include <linux/fpga/fpga-bridge.h>
21 struct fpga_bridge *bridge; member
33 static int op_enable_set(struct fpga_bridge *bridge, bool enable) in op_enable_set() argument
35 struct bridge_stats *stats = bridge->priv; in op_enable_set()
37 stats->enable = enable; in op_enable_set()
43 * Fake FPGA bridge that implements only the enable_set op to track
51 * register_test_bridge() - Register a fake FPGA bridge for testing.
55 * Return: Context of the newly registered FPGA bridge.
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| H A D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0
3 # Makefile for KUnit test suites for the FPGA subsystem
6 obj-$(CONFIG_FPGA_KUNIT_TESTS) += fpga-mgr-test.o fpga-bridge-test.o fpga-region-test.o
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| /linux/Documentation/driver-api/fpga/ |
| H A D | intro.rst | 4 The FPGA subsystem supports reprogramming FPGAs dynamically under
5 Linux. Some of the core intentions of the FPGA subsystems are:
7 * The FPGA subsystem is vendor agnostic.
9 * The FPGA subsystem separates upper layers (userspace interfaces and
11 FPGA.
16 other users. Write the linux-fpga mailing list and maintainers and
23 FPGA Manager
24 ------------
26 If you are adding a new FPGA or a new method of programming an FPGA,
27 this is the subsystem for you. Low level FPGA manager drivers contain
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| H A D | index.rst | 2 FPGA Subsystem
11 fpga-mgr
12 fpga-bridge
13 fpga-region
14 fpga-programming
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| H A D | fpga-programming.rst | 1 In-kernel API for FPGA Programming
5 --------
7 The in-kernel API for FPGA programming is a combination of APIs from
8 FPGA manager, bridge, and regions. The actual function used to
9 trigger FPGA programming is fpga_region_program_fpga().
12 the FPGA manager and bridges. It will:
15 * lock the mutex of the region's FPGA manager
16 * build a list of FPGA bridges if a method has been specified to do so
18 * program the FPGA using info passed in :c:expr:`fpga_region->info`.
19 * re-enable the bridges
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| /linux/drivers/fpga/ |
| H A D | dfl-fme-pr.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for FPGA Management Engine (FME) Partial Reconfiguration
5 * Copyright (C) 2017-2018 Intel Corporation, Inc.
23 #include <linux/fpga/fpga-mgr.h>
24 #include <linux/fpga/fpga
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| H A D | dfl-fme-pr.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Header file for FPGA Management Engine (FME) Partial Reconfiguration Driver
5 * Copyright (C) 2017-2018 Intel Corporation, Inc.
24 * struct dfl_fme_region - FME fpga region data structure
26 * @region: platform device of the FPGA region.
37 * struct dfl_fme_region_pdata - platform data for FME region platform device.
39 * @mgr: platform device of the FPGA manager.
40 * @br: platform device of the FPGA bridge.
50 * struct dfl_fme_bridge - FME fpga bridge data structure
52 * @br: platform device of the FPGA bridge.
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| /linux/drivers/mcb/ |
| H A D | mcb-internal.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
30 * @revision: Revison of Chameleon table in FPGA
36 * @filename: Filename of FPGA bitstream
51 * struct chameleon_gdd - Chameleon General Device Descriptor
53 * @irq: the position in the FPGA's IRQ controller vector
86 * struct chameleon_bdd - Chameleon Bridge Device Descriptor
88 * @irq: the position in the FPGA's IRQ controller vector
95 * @dbar: destination bar from the bus _behind_ the bridge
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| /linux/arch/powerpc/platforms/86xx/ |
| H A D | gef_sbc310.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
12 * NEC fixup adapted from arch/mips/pci/fixup-lm2e.c
26 #include <asm/pci-bridge.h>
56 * There is a simple interrupt handler in the main FPGA, this needs in gef_sbc310_init_irq()
59 cascade_node = of_find_compatible_node(NULL, NULL, "gef,fpga-pic"); in gef_sbc310_init_irq()
61 printk(KERN_WARNING "SBC310: No FPGA PIC\n"); in gef_sbc310_init_irq()
81 regs = of_find_compatible_node(NULL, NULL, "gef,fpga-regs"); in gef_sbc310_setup_arch()
121 /* Return the FPGA revision */
138 ('A' + gef_sbc310_get_board_rev() - 1)); in gef_sbc310_show_cpuinfo()
139 seq_printf(m, "FPGA Revision\t: %u\n", gef_sbc310_get_fpga_rev()); in gef_sbc310_show_cpuinfo()
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| H A D | gef_sbc610.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
12 * NEC fixup adapted from arch/mips/pci/fixup-lm2e.c
26 #include <asm/pci-bridge.h>
56 * There is a simple interrupt handler in the main FPGA, this needs in gef_sbc610_init_irq()
59 cascade_node = of_find_compatible_node(NULL, NULL, "gef,fpga-pic"); in gef_sbc610_init_irq()
61 printk(KERN_WARNING "SBC610: No FPGA PIC\n"); in gef_sbc610_init_irq()
82 regs = of_find_compatible_node(NULL, NULL, "gef,fpga-regs"); in gef_sbc610_setup_arch()
113 /* Return the FPGA revision */
129 ('A' + gef_sbc610_get_board_rev() - 1)); in gef_sbc610_show_cpuinfo()
130 seq_printf(m, "FPGA Revision\t: %u\n", gef_sbc610_get_fpga_rev()); in gef_sbc610_show_cpuinfo()
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| H A D | gef_ppc9a.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
12 * NEC fixup adapted from arch/mips/pci/fixup-lm2e.c
26 #include <asm/pci-bridge.h>
56 * There is a simple interrupt handler in the main FPGA, this needs in gef_ppc9a_init_irq()
59 cascade_node = of_find_compatible_node(NULL, NULL, "gef,fpga-pic-1.00"); in gef_ppc9a_init_irq()
61 printk(KERN_WARNING "PPC9A: No FPGA PIC\n"); in gef_ppc9a_init_irq()
82 regs = of_find_compatible_node(NULL, NULL, "gef,ppc9a-fpga-regs"); in gef_ppc9a_setup_arch()
113 /* Return the FPGA revision */
148 seq_printf(m, "FPGA Revision\t: %u\n", gef_ppc9a_get_fpga_rev()); in gef_ppc9a_show_cpuinfo()
172 /* System clock is 48-MHz Oscillator and EHCI Enabled. */ in gef_ppc9a_nec_fixup()
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| /linux/drivers/net/ethernet/mellanox/mlx5/core/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
17 Core driver for low level functionality of the ConnectX-4 and
18 Connect-IB cards by Mellanox Technologies.
26 and an FPGA chip on one board. If you select this option, the
27 mlx5_core driver will include the Innova FPGA core and allow building
28 sandbox-specific client drivers.
36 Ethernet support in Mellanox Technologies ConnectX-4 NIC.
43 Mellanox MLX5 ethernet hardware-accelerated receive flow steering support,
61 Mellanox Technologies Ethernet Multi-Physical Function Switch (MPFS)
62 support in ConnectX NIC. MPFs is required for when multi-PF configuration
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| /linux/drivers/pci/controller/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
14 controller is part of the South Bridge of the Marvel Armada
22 FPGA.
29 Say Y here if you want PCIe MSI support for the Altera FPGA.
45 system-on-chips, like the Apple M1. This is required for the USB
46 type-A ports, Ethernet, Wi-Fi, and Bluetooth.
102 bool "Cavium Thunder PCIe controller to off-chip devices"
110 bool "Cavium Thunder ECAM controller to on-chip devices on pass-1.x silicon"
115 Say Y here if you want ECAM support for CN88XX-Pass-1.x Cavium Thunder SoCs.
149 in the Intel IXP4xx XScale-based network processor SoC.
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| /linux/arch/powerpc/platforms/85xx/ |
| H A D | ge_imp3a.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
25 #include <asm/pci-bridge.h>
47 if (of_machine_is_compatible("fsl,MPC8572DS-CAMP")) { in ge_imp3a_pic_init()
63 * There is a simple interrupt handler in the main FPGA, this needs in ge_imp3a_pic_init()
66 for_each_node_by_type(np, "interrupt-controller") in ge_imp3a_pic_init()
67 if (of_device_is_compatible(np, "gef,fpga-pic-1.00")) { in ge_imp3a_pic_init()
73 printk(KERN_WARNING "IMP3A: No FPGA PIC\n"); in ge_imp3a_pic_init()
88 if (of_device_is_compatible(np, "fsl,mpc8540-pci") || in ge_imp3a_pci_assign_primary()
89 of_device_is_compatible(np, "fsl,mpc8548-pcie") || in ge_imp3a_pci_assign_primary()
90 of_device_is_compatible(np, "fsl,p2020-pcie")) { in ge_imp3a_pci_assign_primary()
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| H A D | socrates.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
12 * Copyright (c) 2005-2006 DENX Software Engineering
30 #include <asm/pci-bridge.h>
50 np = of_find_compatible_node(NULL, NULL, "abb,socrates-fpga-pic"); in socrates_pic_init()
52 printk(KERN_ERR "Could not find socrates-fpga-pic node\n"); in socrates_pic_init()
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| /linux/arch/powerpc/boot/dts/ |
| H A D | currituck.dts | 11 /dts-v1/;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 dcr-parent = <&{/cpus/cpu@0}>;
27 #address-cells = <1>;
28 #size-cells = <0>;
34 clock-frequency = <1600000000>; // 1.6 GHz
35 timebase-frequency = <100000000>; // 100Mhz
36 i-cache-line-size = <32>;
37 d-cache-line-size = <32>;
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| /linux/arch/mips/loongson2ef/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
8 bool "Lemote Fuloong(2e) mini-PC"
32 Lemote Fuloong(2e) mini-PC board based on the Chinese Loongson-2E CPU and
33 an FPGA northbridge
35 Lemote Fuloong(2e) mini PC have a VIA686B south bridge.
65 Loongson processor and the AMD CS5536 south bridge.
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| /linux/arch/arm64/boot/dts/arm/ |
| H A D | vexpress-v2f-1xv7-ca53x2.dts | 1 // SPDX-License-Identifier: GPL-2.0
6 * V2F-1XV7
8 * Cortex-A53 (2 cores) Soft Macrocell Model
10 * HBI-0247C
13 /dts-v1/;
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include "arm/arm/vexpress-v2m-rs1.dtsi"
19 model = "V2F-1XV7 Cortex-A53x2 SMM";
22 compatible = "arm,vexpress,v2f-1xv7,ca53x2", "arm,vexpress,v2f-1xv7", "arm,vexpress";
23 interrupt-parent = <&gic>;
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