fpga\-bridge (full) in projects: freebsd

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Searched +full:fpga +full:- +full:bridge (Results 1 – 25 of 34) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/fpga/
H A D	fpga-region.txt	`1 FPGA Region Device Tree Binding 6 - Introduction 7 - Terminology 8 - Sequence 9 - FPGA Region 10 - Supported Use Models 11 - Device Tree Examples 12 - Constraints 18 FPGA Region [all...]`
H A D	fpga-region.yaml	`1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/fpga/fpga-region.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: FPGA Region 10 - Michal Simek <michal.simek@amd.com> 14 - Introduction 15 - Terminology 16 - Sequence 17 - FPGA Region [all …]`
H A D	altera-hps2fpga-bridge.txt	`1 Altera FPGA/HPS Bridge Driver 4 - regs : base address and size for AXI bridge module 5 - compatible : Should contain one of: 6 "altr,socfpga-lwhps2fpga-bridge", 7 "altr,socfpga-hps2fpga-bridge", or 8 "altr,socfpga-fpga2hps-bridge" 9 - resets : Phandle and reset specifier for this bridge's reset 10 - clocks : Clocks used by this module. 12 See Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings. 15 fpga_bridge0: fpga-bridge@ff400000 { [all …]`
H A D	xilinx-pr-decoupler.txt	4 decouplers / fpga bridges. 6 changes from passing through the bridge. The controller can also 8 bridge normally. 11 Softcore is compatible with the Xilinx LogiCORE pr-decoupler. 14 from passing through the bridge. The controller safely handles AXI4MM 15 and AXI4-Lite interfaces on a Reconfigurable Partition when it is 24 - compatible : Should contain "xlnx,pr-decoupler-1.00" followed by 25 "xlnx,pr-decoupler" or 26 "xlnx,dfx-axi-shutdown-manager-1.00" followed by 27 "xlnx,dfx-axi-shutdown-manager" [all …]
H A D	altera-fpga2sdram-bridge.txt	`1 Altera FPGA To SDRAM Bridge Driver 4 - compatible : Should contain "altr,socfpga-fpga2sdram-bridge" 6 See Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings. 9 fpga_bridge3: fpga-bridge@ffc25080 { 10 compatible = "altr,socfpga-fpga2sdram-bridge"; 12 bridge-enable = <0>;`
H A D	xlnx,pr-decoupler.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/fpga/xln [all...]`
H A D	fpga-bridge.txt	`1 FPGA Bridge Device Tree Binding 4 - bridge-enable : 0 if driver should disable bridge at startup 5 1 if driver should enable bridge at startup 6 Default is to leave bridge in current state. 9 fpga_bridge3: fpga-bridge@ffc25080 { 10 compatible = "altr,socfpga-fpga2sdram-bridge"; 12 bridge-enable = <0>;`
H A D	altera-freeze-bridge.txt	1 Altera Freeze Bridge Controller Driver 3 The Altera Freeze Bridge Controller manages one or more freeze bridges. 5 changes from passing through the bridge. The controller can also 7 bridge normally. 10 - compatible : Should contain "altr,freeze-bridge-controller" 11 - regs : base address and size for freeze bridge module 13 See Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings. 16 freeze-controller@100000450 { 17 compatible = "altr,freeze-bridge-controller"; 19 bridge-enable = <0>;
/freebsd/sys/contrib/device-tree/src/powerpc/
H A D	currituck.dts	`11 /dts-v1/; 16 #address-cells = <2>; 17 #size-cells = <2>; 20 dcr-parent = <&{/cpus/cpu@0}>; 27 #address-cells = <1>; 28 #size-cells = <0>; 34 clock-frequency = <1600000000>; // 1.6 GHz 35 timebase-frequency = <100000000>; // 100Mhz 36 i-cache-line-size = <32>; 37 d-cache-line-size = <32>; [all …]`
H A D	akebono.dts	`12 /dts-v1/; 17 #address-cells = <2>; 18 #size-cells = <2>; 21 dcr-parent = <&{/cpus/cpu@0}>; 28 #address-cells = <1>; 29 #size-cells = <0>; 35 clock-frequency = <1600000000>; // 1.6 GHz 36 timebase-frequency = <100000000>; // 100Mhz 37 i-cache-line-size = <32>; 38 d-cache-line-size = <32>; [all …]`
H A D	ebony.dts	`14 /dts-v1/; 17 #address-cells = <2>; 18 #size-cells = <1>; 21 dcr-parent = <&{/cpus/cpu@0}>; 31 #address-cells = <1>; 32 #size-cells = <0>; 38 clock-frequency = <0>; // Filled in by zImage 39 timebase-frequency = <0>; // Filled in by zImage 40 i-cache-line-size = <32>; 41 d-cache-line-size = <32>; [all …]`
/freebsd/sys/contrib/device-tree/src/arm64/arm/
H A D	vexpress-v2f-1xv7-ca53x2.dts	`1 // SPDX-License-Identifier: GPL-2.0 6 * V2F-1XV7 8 * Cortex-A53 (2 cores) Soft Macrocell Model 10 * HBI-0247C 13 /dts-v1/; 15 #include <dt-bindings/interrupt-controller/arm-gic.h> 16 #include "arm/arm/vexpress-v2m-rs1.dtsi" 19 model = "V2F-1XV7 Cortex-A53x2 SMM"; 22 compatible = "arm,vexpress,v2f-1xv7,ca53x2", "arm,vexpress,v2f-1xv7", "arm,vexpress"; 23 interrupt-parent = <&gic>; [all …]`
/freebsd/sys/contrib/device-tree/src/arm/intel/socfpga/
H A D	socfpga.dtsi	`1 // SPDX-License-Identifier: GPL-2.0+ 6 #include <dt-bindings/reset/altr,rst-mgr.h> 9 #address-cells = <1>; 10 #size-cells = <1>; 22 #address-cells = <1>; 23 #size-cells = <0>; 24 enable-metho [all...]`
/freebsd/sys/contrib/device-tree/Bindings/arm/
H A D	vexpress-config.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/arm/vexpress-config.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Andre Przywara <andre.przywara@arm.com> 13 This is a system control register block, acting as a bridge to the 16 function and device numbers - see motherboard's TRM for more details. 20 const: arm,vexpress,config-bus 22 arm,vexpress,config-bridge: 31 const: arm,vexpress-muxfpga [all …]`
/freebsd/sys/contrib/device-tree/src/arm/arm/
H A D	integratorcp.dts	`1 // SPDX-License-Identifier: GPL-2.0 6 /dts-v1/; 11 compatible = "arm,integrator-cp"; 18 #address-cells = <1>; 19 #size-cells = <0>; 35 operating-points = <50000 0 38 clock-names = "cpu"; 39 clock-latency = <1000000>; /* 1 ms / 45 ARM DUI 0184B page 7-28 "Integrator/CP922T system clocks" which 50 xtal_codec: clock-24576000 { [all …]`
H A D	versatile-ab.dts	`1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 6 compatible = "arm,versatile-ab"; 7 #address-cells = <1>; 8 #size-cells = <1>; 9 interrupt-parent = <&vic>; 19 stdout-path = &uart0; 27 xtal24mhz: clock-24000000 { 28 #clock-cells = <0>; 29 compatible = "fixed-clock"; [all …]`
H A D	integratorap.dts	`1 // SPDX-License-Identifier: GPL-2.0 6 /dts-v1/; 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/input/input.h> 13 compatible = "arm,integrator-ap"; 16 #address-cells = <1>; 17 #size-cells = <0>; 27 /* compatible = "arm,arm926ej-s"; / 30 The documentation in ARM DUI 0138E page 3-12 states 32 * but painful trial-and-error has proved to me that it [all …]`
H A D	arm-realview-eb.dtsi	`23 #include <dt-bindings/interrupt-controller/irq.h> 24 #include <dt-bindings/gpio/gpio.h> 27 #address-cells = <1>; 28 #size-cells = <1>; 29 compatible = "arm,realview-eb"; 48 vmmc: regulator-vmmc { 49 compatible = "regulator-fixed"; 50 regulator-name = "vmmc"; 51 regulator-min-microvolt = <3300000>; 52 regulator-max-microvolt = <3300000>; [all …]`
H A D	arm-realview-pbx.dtsi	`23 #include <dt-bindings/interrupt-controller/irq.h> 24 #include <dt-bindings/gpio/gpio.h> 27 #address-cells = <1>; 28 #size-cells = <1>; 29 compatible = "arm,realview-pbx"; 49 vmmc: regulator-vmmc { 50 compatible = "regulator-fixed"; 51 regulator-name = "vmmc"; 52 regulator-min-microvolt = <3300000>; 53 regulator-max-microvolt = <3300000>; [all …]`
/freebsd/share/misc/
H A D	pci_vendors	`5 # Date: 2024-11-25 03:15:02 8 # the PCI ID Project at https://pci-ids.ucw.cz/. 14 # (version 2 or higher) or the 3-clause BSD License. 25 # device device_name <-- single tab 26 # subvendor subdevice subsystem_name <-- two tabs 30 # This is a relabelled RTL-8139 31 8139 AT-2500TX V3 Ethernet 33 7a00 Hyper Transport Bridge Controller 41 7a09 PCI-to-PCI Bridge 46 7a10 Hyper Transport Bridge Controller [all …]`
/freebsd/sys/contrib/device-tree/Bindings/pci/
H A D	versatile.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Rob Herring <robh@kernel.org> 13 PCI host controller found on the ARM Versatile PB board's FPGA. 16 - $ref: /schemas/pci/pci-host-bridge.yaml# 20 const: arm,versatile-pci 24 - description: Versatile-specific registers 25 - description: Self Config space 26 - description: Config space [all …]`
H A D	microchip,pcie-host.yaml	1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/microchip,pcie-host.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Microchip PCIe Root Port Bridge Controller 10 - Daire McNamara <daire.mcnamara@microchip.com> 13 - $ref: plda,xpressrich3-axi-common.yaml# 14 - $ref: /schemas/interrupt-controller/msi-controller.yaml# 18 const: microchip,pcie-host-1.0 # PolarFire 22 Fabric Interface Controllers, FICs, are the interface between the FPGA [all …]
/freebsd/sys/dev/bhnd/
H A D	bhnd_ids.h	1 /- 2 SPDX-License-Identifier: ISC 4 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org> 5 * Copyright (c) 1999-2015, Broadcom Corporation 9 * with the dd-wrt project, and the hndsoc.h header distributed with Broadcom's 30 * JEDEC JEP-106 Core Vendor IDs 32 * These are the JEDEC JEP-106 manufacturer ID representions (with ARM's 33 * non-standard 4-bit continutation code), as used in ARM's PrimeCell 38 * will need to convert bus-specific vendor IDs to their BHND_MFGID 39 * JEP-106 equivalents. [all …]
/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A D	mpc8548cds.dtsi	`2 * MPC8548CDS Device Tree Source stub (no addresses or top-level ranges) 37 #address-cells = <1>; 38 #size-cells = <1>; 39 compatible = "cfi-flash"; 41 bank-width = <2>; 42 device-width = <2>; 46 label = "ramdisk-nor"; 51 label = "kernel-nor"; 56 label = "dtb-nor"; 61 label = "env-nor"; [all …]`
/freebsd/sys/contrib/device-tree/Bindings/display/
H A D	xylon,logicvc-display.yaml	1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/display/xylon,logicvc-display.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 - Paul Kocialkowski <paul.kocialkowski@bootlin.com> 16 with Xilinx Zynq-7000 SoCs and Xilinx FPGAs. 18 Because the controller is intended for use in a FPGA, most of the 20 synthesis time. As a result, many of the device-tree bindings are meant to 24 Layers are declared in the "layers" sub-node and have dedicated configuration. 32 - xylon,logicvc-3.02.a-display [all …]