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/linux/Documentation/devicetree/bindings/media/i2c/
H A Dimx219.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Sony 1/4.0-Inch 8Mpixel CMOS Digital Image Sensor
10 - Dave Stevenson <dave.stevenson@raspberrypi.com>
12 description: |-
13 The Sony imx219 is a 1/4.0-inch CMOS active pixel digital image sensor
16 Image data is sent through MIPI CSI-2, which is configured as either 2 or
30 VDIG-supply:
34 VANA-supply:
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H A Dthine,thp7312.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Paul Elder <paul.elder@@ideasonboard.com>
17 MIPI CSI-2 and parallel interfaces. It can also output on either MIPI CSI-2
23 - $ref: /schemas/media/video-interface-devices.yaml#
36 thine,boot-mode:
43 0 is for the SPI/2-wire slave boot, 1 is for the SPI master boot (from
46 reset-gpios:
52 vddcore-supply:
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H A Dtc358743.txt1 * Toshiba TC358743 HDMI-RX to MIPI CSI2-TX Bridge
3 The Toshiba TC358743 HDMI-RX to MIPI CSI2-TX (H2C) is a bridge that converts
4 a HDMI stream to MIPI CSI-2 TX. It is programmable through I2C.
8 - compatible: value should be "toshiba,tc358743"
9 - clocks, clock-names: should contain a phandle link to the reference clock
14 - reset-gpios: gpio phandle GPIO connected to the reset pin
15 - interrupts: GPIO connected to the interrupt pin
16 - data-lanes: should be <1 2 3 4> for four-lane operation,
17 or <1 2> for two-lane operation
18 - clock-lanes: should be <0>
[all …]
H A Disil,isl79987.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Intersil ISL79987 Analog to MIPI CSI-2 decoder
10 - Michael Tretter <m.tretter@pengutronix.de>
11 - Marek Vasut <marex@denx.de>
14 The Intersil ISL79987 is an analog to MIPI CSI-2 decoder which is capable of
15 receiving up to four analog stream and multiplexing them into up to four MIPI
16 CSI-2 virtual channels, using one MIPI clock lane and 1/2 data lanes.
21 - isil,isl79987
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/linux/arch/mips/cavium-octeon/executive/
H A Dcvmx-helper-errata.c7 * Copyright (c) 2003-2008 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
31 * contains functions called by cvmx-helper to workaround known
40 #include <asm/octeon/cvmx-helper-jtag.h>
43 * Due to errata G-720, the 2nd order CDR circuit on CN52XX pass
51 int lane; in __cvmx_helper_errata_qlm_disable_2nd_order_cdr() local
53 /* We need to load all four lanes of the QLM, a total of 1072 bits */ in __cvmx_helper_errata_qlm_disable_2nd_order_cdr()
54 for (lane = 0; lane < 4; lane++) { in __cvmx_helper_errata_qlm_disable_2nd_order_cdr()
56 * Each lane has 268 bits. We need to set in __cvmx_helper_errata_qlm_disable_2nd_order_cdr()
[all …]
/linux/Documentation/devicetree/bindings/display/bridge/
H A Dps8640.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Boichat <drinkcat@chromium.org>
13 The PS8640 is a low power MIPI-to-eDP video format converter supporting
15 device accepts a single channel of MIPI DSI v1.1, with up to four lanes
16 plus clock, at a transmission rate up to 1.5Gbit/sec per lane. The
18 3.24Gbit/sec per lane.
28 powerdown-gpios:
32 reset-gpios:
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H A Drenesas,dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Biju Das <biju.das.jz@bp.renesas.com>
15 up to four data lanes.
18 - $ref: /schemas/display/dsi-controller.yaml#
23 - enum:
24 - renesas,r9a07g044-mipi-dsi # RZ/G2{L,LC}
25 - renesas,r9a07g054-mipi-dsi # RZ/V2L
26 - const: renesas,rzg2l-mipi-dsi
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/linux/drivers/nvdimm/
H A Dbtt.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright (c) 2014-2015, Intel Corporation.
48 * A log group represents one log 'lane', and consists of four log entries.
49 * Two of the four entries are valid entries, and the remaining two are
59 * +-----------------+-----------------+
63 * +-----------------------------------+
67 * +-----------------+-----------------+
70 * +-----------------+-----------------+
74 * +-----------------------------------+
78 * +-----------------+-----------------+
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H A Dbtt.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2014-2015, Intel Corporation.
9 #include <linux/blk-integrity.h>
19 #include <linux/backing-dev.h>
31 return &arena->nd_btt->dev; in to_dev()
36 return offset + nd_btt->initial_offset; in adjust_initial_offset()
42 struct nd_btt *nd_btt = arena->nd_btt; in arena_read_bytes()
43 struct nd_namespace_common *ndns = nd_btt->ndns; in arena_read_bytes()
53 struct nd_btt *nd_btt = arena->nd_btt; in arena_write_bytes()
54 struct nd_namespace_common *ndns = nd_btt->ndns; in arena_write_bytes()
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/linux/Documentation/devicetree/bindings/phy/
H A Dti,phy-j721e-wiz.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Kishon Vijay Abraham I <kishon@ti.com>
16 - ti,j721e-wiz-16g
17 - ti,j721e-wiz-10g
18 - ti,j721s2-wiz-10g
19 - ti,am64-wiz-10g
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H A Dxlnx,zynqmp-psgtr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/xlnx,zynqmp-psgtr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
14 GTR provides four lanes and is used by USB, SATA, PCIE, Display port and
18 "#phy-cells":
23 - description: The GTR lane
26 - description: The PHY type
28 - PHY_TYPE_DP
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/linux/Documentation/devicetree/bindings/pci/
H A Dti-pci.txt4 - compatible: Should be "ti,dra7-pcie" for RC (deprecated)
5 Should be "ti,dra7-pcie-ep" for EP (deprecated)
6 Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode
7 Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode
8 Should be "ti,dra726-pcie-rc" for dra72x in RC mode
9 Should be "ti,dra726-pcie-ep" for dra72x in EP mode
10 - phys : list of PHY specifiers (used by generic PHY framework)
11 - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
13 - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
15 - num-lanes as specified in ../snps,dw-pcie.yaml
[all …]
H A Dmvebu-pci.txt5 - compatible: one of the following values:
6 marvell,armada-370-pcie
7 marvell,armada-xp-pcie
8 marvell,dove-pcie
9 marvell,kirkwood-pcie
10 - #address-cells, set to <3>
11 - #size-cells, set to <2>
12 - #interrupt-cells, set to <1>
13 - bus-range: PCI bus numbers covered
14 - device_type, set to "pci"
[all …]
/linux/drivers/phy/tegra/
H A Dxusb-tegra186.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved.
21 #define HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? (11 + (x - 1) * 6) : 0)
280 writel(value, priv->ao_regs + offset); in ao_writel()
285 return readl(priv->ao_regs + offset); in ao_readl()
304 return ERR_PTR(-ENOMEM); in tegra186_usb2_lane_probe()
306 INIT_LIST_HEAD(&usb2->base.list); in tegra186_usb2_lane_probe()
307 usb2->base.soc = &pad->soc->lanes[index]; in tegra186_usb2_lane_probe()
308 usb2->base.index = index; in tegra186_usb2_lane_probe()
309 usb2->base.pad = pad; in tegra186_usb2_lane_probe()
[all …]
H A Dxusb-tegra210.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
27 ((x) ? (11 + ((x) - 1) * 6) : 0)
447 static int tegra210_usb3_lane_map(struct tegra_xusb_lane *lane) in tegra210_usb3_lane_map() argument
451 for (map = tegra210_usb3_map; map->type; map++) { in tegra210_usb3_lane_map()
452 if (map->index == lane->index && in tegra210_usb3_lane_map()
453 strcmp(map->type, lane->pad->soc->name) == 0) { in tegra210_usb3_lane_map()
454 dev_dbg(lane->pad->padctl->dev, "lane = %s map to port = usb3-%d\n", in tegra210_usb3_lane_map()
455 lane->pad->soc->lanes[lane->index].name, map->port); in tegra210_usb3_lane_map()
456 return map->port; in tegra210_usb3_lane_map()
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/linux/drivers/gpu/drm/bridge/
H A Dtc358764.c1 // SPDX-License-Identifier: GPL-2.0
24 #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
30 #define PPI_LANEENABLE 0x0134 /* Enables each lane */
32 #define PPI_D0S_CLRSIPOCOUNT 0x0164 /* Assertion timer for Lane 0 */
33 #define PPI_D1S_CLRSIPOCOUNT 0x0168 /* Assertion timer for Lane 1 */
34 #define PPI_D2S_CLRSIPOCOUNT 0x016C /* Assertion timer for Lane 2 */
35 #define PPI_D3S_CLRSIPOCOUNT 0x0170 /* Assertion timer for Lane 3 */
39 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */
40 #define DSI_LANEENABLE 0x0210 /* Enables each lane */
121 #define SYS_RST_I2CS BIT(0) /* Reset I2C-Slave controller */
[all …]
/linux/tools/perf/pmu-events/arch/x86/icelakex/
H A Duncore-io.json114 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-7",
121 "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0-7",
133 …ompletions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
145 …ompletions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
157 …ompletions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
169 …ompletions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
181 …ompletions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
193 …ompletions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
205 …ompletions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
217 …ompletions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
[all …]
/linux/drivers/gpu/drm/i915/display/
H A Dintel_dpio_phy.c2 * Copyright © 2014-2016 Intel Corporation
45 * IOSF-SB port.
48 * houses a common lane part which contains the PLL and other common
49 * logic. CH0 common lane also contains the IOSF-SB logic for the
59 * each spline is made up of one Physical Access Coding Sub-Layer
61 * and four TX lanes. The TX lanes are used as DP lanes or TMDS
64 * Additionally the PHY also contains an AUX lane with AUX blocks
70 * Generally on VLV/CHV the common lane corresponds to the pipe and
103 * ---------------------------------
106 * |---------------|---------------| Display PHY
[all …]
/linux/arch/arm/boot/dts/marvell/
H A Darmada-xp-synology-ds414.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot
12 * were delivered with an older version of u-boot that left internal
17 * installing it from u-boot prompt) or adjust the Devive Tree
21 /dts-v1/;
23 #include <dt-bindings/input/input.h>
24 #include <dt-bindings/gpio/gpio.h>
25 #include "armada-xp-mv78230.dtsi"
29 compatible = "synology,ds414", "marvell,armadaxp-mv78230",
30 "marvell,armadaxp", "marvell,armada-370-xp";
[all …]
/linux/drivers/pci/controller/
H A Dpcie-rockchip.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Author: Shawn Lin <shawn.lin@rock-chips.com>
8 * Wenrui Li <wenrui.li@rock-chips.com>
25 #include "pcie-rockchip.h"
29 struct device *dev = rockchip->dev; in rockchip_pcie_parse_dt()
31 struct device_node *node = dev->of_node; in rockchip_pcie_parse_dt()
35 if (rockchip->is_rc) { in rockchip_pcie_parse_dt()
38 "axi-base"); in rockchip_pcie_parse_dt()
39 rockchip->reg_base = devm_pci_remap_cfg_resource(dev, regs); in rockchip_pcie_parse_dt()
40 if (IS_ERR(rockchip->reg_base)) in rockchip_pcie_parse_dt()
[all …]
/linux/tools/perf/pmu-events/arch/x86/snowridgex/
H A Duncore-io.json13 …, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
29 …, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
145 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-7",
152 "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0-7",
164 …ompletions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
176 …ompletions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
188 …ompletions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
200 …ompletions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
212 …ompletions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
224 …ompletions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
[all …]
/linux/arch/powerpc/sysdev/
H A Dfsl_rio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * - fixed maintenance access routines, check for aligned access
11 * - Added Port-Write message handling
12 * - Added Machine Check exception handling
24 #include <linux/dma-mapping.h>
40 #undef DEBUG_PW /* Port-Write debugging */
79 "3: li %1,-1\n" \
85 : "b" (addr), "i" (-EFAULT), "0" (err))
114 entry = search_exception_tables(regs->nip); in fsl_rio_mcheck_exception()
116 pr_debug("RIO: %s - MC Exception handled\n", in fsl_rio_mcheck_exception()
[all …]
/linux/include/drm/
H A Ddrm_mipi_dsi.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2012-2013, Samsung Electronics, Co., Ltd.
25 * struct mipi_dsi_msg - read/write DSI buffer
50 * struct mipi_dsi_packet - represents a MIPI DSI packet in protocol format
52 * @header: the four bytes that make up the header (Data ID, Word Count or
68 * struct mipi_dsi_host_ops - DSI bus operations
100 * struct mipi_dsi_host - DSI host device
125 /* enable hsync-end packets in vsync-pulse and v-porch area */
127 /* disable hfront-porch area */
129 /* disable hback-porch area */
[all …]
/linux/drivers/media/i2c/
H A Dimx274.c1 // SPDX-License-Identifier: GPL-2.0
3 * imx274.c - IMX274 CMOS Image Sensor driver
23 #include <linux/v4l2-mediabus.h>
26 #include <media/v4l2-ctrls.h>
27 #include <media/v4l2-device.h>
28 #include <media/v4l2-fwnode.h>
29 #include <media/v4l2-subdev.h>
49 #define IMX274_GAIN_SHIFT_MASK ((1 << IMX274_GAIN_SHIFT) - 1)
59 / (2048 - IMX274_GAIN_REG_MAX))
76 * register SHR is limited to (SVR value + 1) x VMAX value - 4
[all …]
/linux/include/uapi/misc/
H A Dxilinx_sdfec.h1 /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
3 * Xilinx SD-FEC
26 (XSDFEC_LDPC_SC_TABLE_ADDR_HIGH - XSDFEC_LDPC_SC_TABLE_ADDR_BASE)
28 (XSDFEC_LDPC_LA_TABLE_ADDR_HIGH - XSDFEC_LDPC_LA_TABLE_ADDR_BASE)
30 (XSDFEC_LDPC_QC_TABLE_ADDR_HIGH - XSDFEC_LDPC_QC_TABLE_ADDR_BASE)
33 * enum xsdfec_code - Code Type.
47 * enum xsdfec_order - Order
49 * @XSDFEC_OUT_OF_ORDER: Out-of-order execution of blocks.
60 * enum xsdfec_turbo_alg - Turbo Algorithm Type.
61 * @XSDFEC_MAX_SCALE: Max Log-Map algorithm with extrinsic scaling. When
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