| /freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/ |
| H A D | ti,c64x+megamod-pic.txt | 2 -------------------
8 Priority 2 and 3 are reserved. Priority 4-15 are used for interrupt
12 --------------------
13 - compatible: Should be "ti,c64x+core-pic";
14 - #interrupt-cells: <1>
17 ------------------------------
18 Single cell specifying the core interrupt priority level (4-15) where
22 -------
23 core_pic: interrupt-controller@0 {
24 interrupt-controller;
[all …]
|
| H A D | img,pdc-intc.txt | 10 - compatible: Specifies the compatibility list for the interrupt controller.
11 The type shall be <string> and the value shall include "img,pdc-intc".
13 - reg: Specifies the base PDC physical address(s) and size(s) of the
14 addressable register space. The type shall be <prop-encoded-array>.
16 - interrupt-controller: The presence of this property identifies the node
19 - #interrupt-cells: Specifies the number of cells needed to encode an
22 - num-perips: Number of waking peripherals.
24 - num-syswakes: Number of SysWake inputs.
26 - interrupts: List of interrupt specifiers. The first specifier shall be the
34 - <1st-cell>: The interrupt-number that identifies the interrupt source.
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/power/supply/ |
| H A D | sbs,sbs-manager.txt | 1 Binding for sbs-manager
4 - compatible: "<vendor>,<part-number>", "sbs,sbs-charger" as fallback. The part
7 - reg: integer, i2c address of the device. Should be <0xa>.
9 - gpio-controller: Marks the port as GPIO controller.
10 See "gpio-specifier" in .../devicetree/bindings/gpio/gpio.txt.
11 - #gpio-cells: Should be <2>. The first cell is the pin number, the second cell
13 See "gpio-specifier" in .../devicetree/bindings/gpio/gpio.txt.
15 From OS view the device is basically an i2c-mux used to communicate with up to
16 four smart battery devices at address 0xb. The driver actually implements this
17 behaviour. So standard i2c-mux nodes can be used to register up to four slave
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/dma/ |
| H A D | snps-dma.txt | 4 - compatible: "snps,dma-spear1340"
5 - reg: Address range of the DMAC registers
6 - interrupt: Should contain the DMAC interrupt number
7 - dma-channels: Number of channels supported by hardware
8 - dma-requests: Number of DMA request lines supported, up to 16
9 - dma-masters: Number of AHB masters supported by the controller
10 - #dma-cells: must be <3>
11 - chan_allocation_order: order of allocation of channel, 0 (default): ascending,
13 - chan_priority: priority of channels. 0 (default): increase from chan 0->n, 1:
14 increase from chan n->0
[all …]
|
| H A D | renesas,rzn1-dmamux.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/renesas,rzn1-dmamux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 - $ref: dma-router.yaml#
17 const: renesas,rzn1-dmamux
23 '#dma-cells':
26 The first four cells are dedicated to the master DMA controller. The fifth
27 cell gives the DMA mux bit index that must be set starting from 0. The
[all …]
|
| H A D | st,stm32-dma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/st,stm32-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The STM32 DMA is a general-purpose direct memory access controller capable of
13 described in the dma.txt file, using a four-cell specifier for each
14 channel: a phandle to the DMA controller plus the following four integer cells:
19 -bit 9: Peripheral Increment Address
22 -bit 10: Memory Increment Address
25 -bit 15: Peripheral Increment Offset Size
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | cavium-mix.txt | 4 - compatible: "cavium,octeon-5750-mix"
9 - reg: The base addresses of four separate register banks. The first
15 - cell-index: A single cell specifying which portion of the shared
18 - interrupts: Two interrupt specifiers. The first is the MIX
21 - phy-handle: Optional, see ethernet.txt file in the same directory.
25 compatible = "cavium,octeon-5750-mix";
30 cell-index = <1>;
32 local-mac-address = [ 00 0f b7 10 63 54 ];
33 phy-handle = <&phy1>;
|
| /freebsd/sys/contrib/device-tree/Bindings/gpio/ |
| H A D | cavium-octeon-gpio.txt | 4 - compatible: "cavium,octeon-3860-gpio"
8 - reg: The base address of the GPIO unit's register bank.
10 - gpio-controller: This is a GPIO controller.
12 - #gpio-cells: Must be <2>. The first cell is the GPIO pin.
14 - interrupt-controller: The GPIO controller is also an interrupt
18 - #interrupt-cells: Must be <2>. The first cell is the GPIO pin
19 connected to the interrupt source. The second cell is the interrupt
20 triggering protocol and may have one of four values:
21 1 - edge triggered on the rising edge.
22 2 - edge triggered on the falling edge
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/clock/ |
| H A D | stericsson,u8500-clks.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/stericsson,u8500-clks.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson DB8500 (U8500) clocks
10 - Ulf Hansson <ulf.hansson@linaro.org>
11 - Linus Walleij <linus.walleij@linaro.org>
14 DB8500 digital baseband system-on-chip and its siblings such as
16 itself, not off-chip clocks. There are four different on-chip
17 clocks - RTC (32 kHz), CPU clock (SMP TWD), PRCMU (power reset and
[all …]
|
| H A D | pistachio-clock.txt | 4 Pistachio has four clock controllers (core clock, peripheral clock, peripheral
6 from the device-tree.
9 ----------------
12 defined with the following clock-output-names:
13 - "xtal": External 52Mhz oscillator (required)
14 - "audio_clk_in": Alternate audio reference clock (optional)
15 - "enet_clk_in": Alternate ethernet PHY clock (optional)
18 ----------------------
21 co-processor), audio, and several peripherals.
24 - compatible: Must be "img,pistachio-clk".
[all …]
|
| H A D | microchip,mpfs-ccc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/microchip,mpfs-ccc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Conor Dooley <conor.dooley@microchip.com>
14 these blocks contains two PLLs and 2 DLLs & are located in the four corners of
16 https://onlinedocs.microchip.com/pr/GUID-8F0CC4C0-0317-4262-89CA-CE7773ED1931-en-US-1/index.html
20 const: microchip,mpfs-ccc
24 - description: PLL0's control registers
25 - description: PLL1's control registers
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/rtc/ |
| H A D | qcom-pm8xxx-rtc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rtc/qcom-pm8xxx-rt
[all...] |
| /freebsd/sys/contrib/device-tree/Bindings/sound/ |
| H A D | cirrus,madera.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - patches@opensource.cirrus.com
21 include/dt-bindings/sound/madera.h
26 - $ref: dai-common.yaml#
29 '#sound-dai-cells':
31 The first cell indicating the audio interface.
37 of 24 cells, with four cells per input in the order INnAL,
38 INnAR INnBL INnBR. For non-muxed inputs the first two cells
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/mfd/ |
| H A D | ti,lp87561-q1.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/ti,lp87561-q
[all...] |
| H A D | ti,lp87524-q1.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/ti,lp87524-q
[all...] |
| /freebsd/sys/contrib/device-tree/Bindings/phy/ |
| H A D | fsl,imx8qm-lvds-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8qm-lvds-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
14 It converts two groups of four 7/10 bits of CMOS data into two
15 groups of four data lanes of LVDS data streams. A phase-locked
30 - fsl,imx8qm-lvds-phy
31 - mixel,28fdsoi-lvds-1250-8ch-tx-pll
33 "#phy-cells":
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/thermal/ |
| H A D | thermal.txt | 15 - thermal sensors: devices which may be used to take temperature
17 - cooling devices: devices which may be used to dissipate heat.
18 - trip points: describe key temperatures at which cooling is recommended. The
20 - cooling maps: used to describe links between trip points and cooling devices;
21 - thermal zones: used to describe thermal data within the hardware;
33 - #thermal-sensor-cells: Used to provide sensor device specific information
35 Size: one cell nodes with only one sensor, and at least 1 on nodes
62 - #cooling-cells: Used to provide cooling device specific information
64 Size: one cell to specify minimum and maximum cooling state used
65 in the reference. The first cell is the minimum
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/soc/fsl/cpm_qe/ |
| H A D | gpio.txt | 1 Every GPIO controller node must have #gpio-cells property defined,
2 this information will be used to translate gpio-specifiers.
10 - compatible : "fsl,cpm1-pario-bank-a", "fsl,cpm1-pario-bank-b",
11 "fsl,cpm1-pario-bank-c", "fsl,cpm1-pario-bank-d",
12 "fsl,cpm1-pario-bank-e", "fsl,cpm2-pario-bank"
13 - #gpio-cells : Should be two. The first cell is the pin number and the
14 second cell is used to specify optional parameters (currently unused).
15 - gpio-controller : Marks the port as GPIO controller.
17 - fsl,cpm1-gpio-irq-mask : For banks having interrupt capability (like port C
20 - interrupts : This property provides the list of interrupt for each GPIO having
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/dma/stm32/ |
| H A D | st,stm32-dma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/stm32/st,stm32-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The STM32 DMA is a general-purpose direct memory access controller capable of
13 described in the dma.txt file, using a four-cell specifier for each
14 channel: a phandle to the DMA controller plus the following four integer cells:
19 -bit 9: Peripheral Increment Address
22 -bit 10: Memory Increment Address
25 -bit 15: Peripheral Increment Offset Size
[all …]
|
| /freebsd/share/dict/ |
| H A D | web2a | 12 A-b-c book
13 A-b-c method
14 abdomino-uterotomy
15 Abdul-baha
16 a-be
20 able-bodied
21 able-bodiedness
22 able-minded
23 able-mindedness
27 Abor-miri
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/usb/ |
| H A D | usb-device.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/usb-device.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
15 http://www.devicetree.org/open-firmware/bindings/usb/usb-1_0.ps
17 Four types of device-tree nodes are defined: "host-controller nodes"
31 pattern: "^usb[0-9a-f]{1,4},[0-9a-f]{1,4}$"
41 description: the number of the USB hub port or the USB host-controller
42 port to which this device is attached. The range is 1-255.
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/mailbox/ |
| H A D | allwinner,sun6i-a31-msgbox.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mailbox/allwinner,sun6i-a31-msgbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Samuel Holland <samuel@sholland.org>
14 two-user mailbox controller containing 8 unidirectional FIFOs. An interrupt
17 hold four 32-bit messages; when a FIFO is full, clients must wait before
20 Refer to ./mailbox.txt for generic information about mailbox device-tree
26 - items:
27 - enum:
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/display/ |
| H A D | mipi-dsi-bus.txt | 5 communication between a host and up to four peripherals. This document will
8 This document describes DSI bus-specific properties only or defines existing
25 - #address-cells: The number of cells required to represent an address on the
26 bus. DSI peripherals are addressed using a 2-bit virtual channel number, so
29 - #size-cells: Should be 0. There are cases where it makes sense to use a
33 - clock-master: boolean. Should be enabled if the host is being used in
43 ------------------------------------------------------
49 device-specific properties.
52 - reg: The virtual channel number of a DSI peripheral. Must be in the range
57 - The reg property can take multiple entries, one for each virtual channel
[all …]
|
| H A D | arm,pl11x.txt | 7 - compatible: must be one of:
11 - reg: base address and size of the control registers block
13 - interrupt-names: either the single entry "combined" representing a
14 combined interrupt output (CLCDINTR), or the four entries
18 - interrupts: contains an interrupt specifier for each entry in
19 interrupt-names
21 - clock-names: should contain "clcdclk" and "apb_pclk"
23 - clocks: contains phandle and clock specifier pairs for the entries
24 in the clock-names property. See
25 Documentation/devicetree/bindings/clock/clock-bindings.txt
[all …]
|
| /freebsd/contrib/ncurses/man/ |
| H A D | curs_inwstr.3x | 2 .\" Copyright 2018-2023,2024 Thomas E. Dickey *
3 .\" Copyright 2002-2012,2017 Free Software Foundation, Inc. *
31 .TH curs_inwstr 3X 2024-04-20 "ncurses @NCURSES_MAJOR@.@NCURSES_MINOR@" "Library calls"
54 \fB\%mvwinnwstr\fP \-
55 get a wide-character string from a \fIcurses\fR window
74 The four functions with \fIn\fP as the last argument return
112 Each cell in the window holds a complex character
113 (a spacing character and zero or more non-spacing characters)
|