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/linux/Documentation/devicetree/bindings/phy/
H A Dmediatek,tphy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/mediatek,tphy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek T-PHY Controller
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 The T-PHY controller supports physical layer functionality for a number of
17 Layout differences of banks between T-PHY V1 (mt8173/mt2701) and
18 T-PHY V2 (mt2712) / V3 (mt8195) when works on USB mode:
19 -----------------------------------
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/linux/Documentation/networking/device_drivers/ethernet/davicom/
H A Ddm9000.rst1 .. SPDX-License-Identifier: GPL-2.0
9 Ben Dooks <ben@simtec.co.uk> <ben-linux@fluff.org>
13 ------------
15 This file describes how to use the DM9000 platform-device based network driver
25 ----------------------------
37 An example from arch/arm/mach-s3c/mach-bast.c is::
91 -------------
94 device, whether or not an external PHY is attached to the device and
113 The chip is connected to an external PHY.
122 Switch to using the simpler PHY polling method which does not
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/linux/arch/mips/include/asm/mach-bcm63xx/
H A Dbcm63xx_dev_enet.h1 /* SPDX-License-Identifier: GPL-2.0 */
21 /* or fill phy info to use an external one */
26 /* if has_phy, use autonegotiated pause parameters or force
50 /* DMA engine has internal SRAM */
68 #define ENETSW_PORTS_6328 5 /* 4 FE PHY + 1 RGMII */
69 #define ENETSW_PORTS_6368 6 /* 4 FE PHY + 2 RGMII */
98 /* DMA engine has internal SRAM */
/linux/drivers/phy/
H A Dphy-xgene.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AppliedMicro X-Gene Multi-purpose PHY driver
10 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
11 * The first PLL clock macro is used for internal reference clock. The second
12 * PLL clock macro is used to generate the clock for the PHY. This driver
13 * configures the first PLL CMU, the second PLL CMU, and programs the PHY to
15 * required if internal clock is enabled.
19 * -----------------
20 * | Internal | |------|
21 * | Ref PLL CMU |----| | ------------- ---------
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/linux/net/core/
H A Dselftests.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/phy.h>
66 size = attr->size + NET_TEST_PKT_SIZE; in net_test_get_skb()
68 if (attr->tcp) in net_test_get_skb()
73 if (attr->max_size && attr->max_size > size) in net_test_get_skb()
74 size = attr->max_size; in net_test_get_skb()
80 prefetchw(skb->data); in net_test_get_skb()
85 skb_set_network_header(skb, skb->len); in net_test_get_skb()
88 skb_set_transport_header(skb, skb->len); in net_test_get_skb()
89 if (attr->tcp) in net_test_get_skb()
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/linux/arch/arm64/boot/dts/marvell/
H A Dcn9130-cf-pro.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2024 Josua Mayer <josua@solid-run.com>
9 /dts-v1/;
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/leds/common.h>
15 #include "cn9130-sr-som.dtsi"
16 #include "cn9130-cf.dtsi"
20 compatible = "solidrun,cn9130-clearfog-pro",
21 "solidrun,cn9130-sr-som", "marvell,cn9130";
23 gpio-keys {
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/linux/arch/arm/boot/dts/samsung/
H A Ds3c6410-smdk6410.dts1 // SPDX-License-Identifier: GPL-2.0
11 /dts-v1/;
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
31 fin_pll: oscillator-0 {
32 compatible = "fixed-clock";
33 clock-frequency = <12000000>;
34 clock-output-names = "fin_pll";
35 #clock-cells = <0>;
38 xusbxti: oscillator-1 {
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H A Dexynos5410-smdk5410.dts1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/irq.h>
27 stdout-path = "serial2:115200n8";
31 compatible = "fixed-clock";
32 clock-frequency = <24000000>;
33 clock-output-names = "fin_pll";
34 #clock-cells = <0>;
37 pmic_ap_clk: pmic-ap-clk {
39 compatible = "fixed-clock";
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/linux/Documentation/networking/device_drivers/ethernet/stmicro/
H A Dstmmac.rst1 .. SPDX-License-Identifier: GPL-2.0+
13 - In This Release
14 - Feature List
15 - Kernel Configuration
16 - Command Line Parameters
17 - Driver Information and Notes
18 - Debug Information
19 - Support
33 (and older) and DesignWare(R) Cores Ethernet Quality-of-Service version 4.0
35 DesignWare(R) Cores XGMAC - 10G Ethernet MAC and DesignWare(R) Cores
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/linux/Documentation/networking/
H A Dsfp-phylink.rst1 .. SPDX-License-Identifier: GPL-2.0
10 phylink is a mechanism to support hot-pluggable networking modules
11 directly connected to a MAC without needing to re-initialise the
12 adapter on hot-plug events.
14 phylink supports conventional phylib-based setups, fixed link setups
23 1. PHY mode
25 In PHY mode, we use phylib to read the current link settings from
26 the PHY, and pass them to the MAC driver. We expect the MAC driver
32 Fixed mode is the same as PHY mode as far as the MAC driver is
35 3. In-band mode
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/linux/drivers/net/ethernet/marvell/
H A Dsky2.h1 /* SPDX-License-Identifier: GPL-2.0 */
30 /* Yukon-2 */
32 PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
33 PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */
34 PCI_SW_PWR_ON_RST= 1<<30, /* SW Power on Reset (Yukon-EX) */
35 PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
36 PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
37 PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
38 PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
44 PCI_FORCE_PEX_L1 = 1<<5, /* Force to PEX L1 */
[all …]
/linux/drivers/net/ethernet/intel/e1000e/
H A Dmac.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
9 * e1000e_get_bus_info_pcie - Get PCIe bus information
18 struct pci_dev *pdev = hw->adapter->pdev; in e1000e_get_bus_info_pcie()
19 struct e1000_mac_info *mac = &hw->mac; in e1000e_get_bus_info_pcie()
20 struct e1000_bus_info *bus = &hw->bus; in e1000e_get_bus_info_pcie()
24 bus->width = e1000_bus_width_unknown; in e1000e_get_bus_info_pcie()
27 bus->width = (enum e1000_bus_width)FIELD_GET(PCI_EXP_LNKSTA_NLW, in e1000e_get_bus_info_pcie()
31 mac->ops.set_lan_id(hw); in e1000e_get_bus_info_pcie()
37 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
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/linux/drivers/net/dsa/
H A Dmv88e6060.c1 // SPDX-License-Identifier: GPL-2.0+
3 * net/dsa/mv88e6060.c - Driver for Marvell 88e6060 switch chips
4 * Copyright (c) 2008-2009 Marvell Semiconductor
13 #include <linux/phy.h>
19 return mdiobus_read_nested(priv->bus, priv->sw_addr + addr, reg); in reg_read()
24 return mdiobus_write_nested(priv->bus, priv->sw_addr + addr, reg, val); in reg_write()
92 return -ETIMEDOUT; in mv88e6060_switch_reset()
121 if (dsa_is_unused_port(priv->ds, p)) in mv88e6060_setup_port()
124 /* Do not force flow control, disable Ingress and Egress in mv88e6060_setup_port()
130 dsa_is_cpu_port(priv->ds, p) ? in mv88e6060_setup_port()
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H A Dbcm_sf2.c1 // SPDX-License-Identifier: GPL-2.0-or-later
13 #include <linux/phy.h>
37 switch (priv->type) { in bcm_sf2_reg_rgmii_cntrl()
76 switch (priv->type) { in bcm_sf2_reg_led_base()
99 switch (priv->type) { in bcm_sf2_port_override_offset()
108 WARN_ONCE(1, "Unsupported device: %d\n", priv->type); in bcm_sf2_port_override_offset()
121 for (port = 0; port < ds->num_ports; port++) { in bcm_sf2_num_active_ports()
124 if (priv->port_sts[port].enabled) in bcm_sf2_num_active_ports()
145 if (ports_active == 0 || !priv->clk_mdiv) in bcm_sf2_recalc_clock()
154 new_rate = rate_table[ports_active - 1]; in bcm_sf2_recalc_clock()
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/linux/drivers/phy/amlogic/
H A Dphy-meson-axg-mipi-dphy.c1 // SPDX-License-Identifier: GPL-2.0
20 #include <linux/phy/phy.h>
23 /* [31] soft reset for the phy.
44 * [3] force data byte lane in stop mode.
45 * [2] force data byte lane 0 in receiver mode.
46 * [1] write 1 to sync the txclkesc input. the internal logic have to
172 struct phy *analog;
183 static int phy_meson_axg_mipi_dphy_init(struct phy *phy) in phy_meson_axg_mipi_dphy_init() argument
185 struct phy_meson_axg_mipi_dphy_priv *priv = phy_get_drvdata(phy); in phy_meson_axg_mipi_dphy_init()
188 ret = phy_init(priv->analog); in phy_meson_axg_mipi_dphy_init()
[all …]
/linux/include/linux/
H A Dbrcmphy.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <linux/phy.h>
7 /* All Broadcom Ethernet switches have a pseudo-PHY at address 30 which is used
8 * to configure the switch internal registers via MDIO accesses.
84 #define MII_BCM54XX_ECR_IF 0x0800 /* Interrupt force */
94 #define MII_BCM54XX_EXP_SEL_WOL 0x0e00 /* Wake-on-LAN expansion select register */
111 #define MII_BCM54XX_INT_ANPR 0x0400 /* Auto-negotiation page received */
131 * AUXILIARY CONTROL SHADOW ACCESS REGISTERS. (PHY REG 0x18)
212 /* 01010: Auto Power-Down */
231 /* 10011: SerDes 100-FX Control Register */
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/linux/drivers/net/ethernet/sun/
H A Dsunhme.c1 // SPDX-License-Identifier: GPL-2.0
10 * 2000/11/11 Willy Tarreau <willy AT meta-x.org>
11 * - port to non-sparc architectures. Tested only on x86 and
13 * - ability to specify the MAC address at module load time by passing this
20 #include <linux/dma-mapping.h>
83 /* "Auto Switch Debug" aka phy debug */
111 tlp->tstamp = (unsigned int)jiffies;
112 tlp->tx_new = hp->tx_new;
113 tlp->tx_old = hp->tx_old;
114 tlp->action = a;
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H A Dsunhme.h1 /* SPDX-License-Identifier: GPL-2.0 */
38 #define GREG_STAT_ACNTEXP 0x00000004 /* Align-error counter expired */
39 #define GREG_STAT_CCNTEXP 0x00000008 /* CRC-error counter expired */
40 #define GREG_STAT_LCNTEXP 0x00000010 /* Length-error counter expired */
42 #define GREG_STAT_CVCNTEXP 0x00000040 /* Code-violation counter expired */
46 #define GREG_STAT_MAXPKTERR 0x00000400 /* Max-packet size error */
47 #define GREG_STAT_NCNTEXP 0x00000800 /* Normal-collision counter expired */
48 #define GREG_STAT_ECNTEXP 0x00001000 /* Excess-collision counter expired */
49 #define GREG_STAT_LCCNTEXP 0x00002000 /* Late-collision counter expired */
50 #define GREG_STAT_FCNTEXP 0x00004000 /* First-collision counter expired */
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/linux/drivers/phy/samsung/
H A Dphy-exynos5-usbdrd.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Samsung Exynos5 SoC series USB DRD PHY driver
5 * Phy provider for USB 3.0 DRD controller on Exynos5 SoC series
19 #include <linux/phy/phy.h>
25 #include <linux/soc/samsung/exynos-regs-pmu.h>
29 /* Exynos USB PHY registers */
39 /* USB 3.2 DRD 4nm PHY link controller registers */
54 /* Exynos5: USB 3.0 DRD PHY registers */
157 /* USB 3.0 DRD PHY SS Function Control Reg; accessed by CR_PORT */
176 /* Exynos7870: USB DRD PHY registers */
[all …]
/linux/drivers/phy/allwinner/
H A Dphy-sun6i-mipi-dphy.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2017-2018 Bootlin
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
17 #include <linux/phy/phy.h>
18 #include <linux/phy/phy-mipi-dphy.h>
21 #define SUN6I_DPHY_GCTL_LANE_NUM(n) ((((n) - 1) & 3) << 4)
193 struct phy *phy; member
200 static int sun6i_dphy_init(struct phy *phy) in sun6i_dphy_init() argument
202 struct sun6i_dphy *dphy = phy_get_drvdata(phy); in sun6i_dphy_init()
204 reset_control_deassert(dphy->reset); in sun6i_dphy_init()
[all …]
/linux/Documentation/devicetree/bindings/mmc/
H A Darasan,sdhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Adrian Hunter <adrian.hunter@intel.com>
13 - $ref: mmc-controller.yaml#
14 - if:
18 const: arasan,sdhci-5.1
21 - phys
22 - phy-names
23 - if:
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/linux/drivers/net/ethernet/intel/igc/
H A Digc_mac.c1 // SPDX-License-Identifier: GPL-2.0
11 * igc_disable_pcie_master - Disables PCI-express master access
14 * Returns 0 (0) if successful, else returns -10
15 * (-IGC_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
18 * Disables PCI-Express master access and verifies there are no pending
36 timeout--; in igc_disable_pcie_master()
41 ret_val = -IGC_ERR_MASTER_REQUESTS_PENDING; in igc_disable_pcie_master()
50 * igc_init_rx_addrs - Initialize receive addresses
66 hw->mac.ops.rar_set(hw, hw->mac.addr, 0); in igc_init_rx_addrs()
68 /* Zero out the other (rar_entry_count - 1) receive addresses */ in igc_init_rx_addrs()
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/linux/arch/arm/boot/dts/st/
H A Dstm32mp157c-lxa-mc1.dts1 /* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) */
3 * Copyright (C) 2020 STMicroelectronics - All Rights Reserved
7 /dts-v1/;
10 #include "stm32mp15xx-osd32.dtsi"
11 #include "stm32mp15xxac-pinctrl.dtsi"
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/pwm/pwm.h>
17 model = "Linux Automation MC-1 board";
18 compatible = "lxa,stm32mp157c-mc1", "oct,stm32mp15xx-osd32", "st,stm32mp157";
28 compatible = "pwm-backlight";
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/linux/drivers/gpu/drm/bridge/synopsys/
H A Ddw-hdmi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * DesignWare High-Definition Multimedia Interface (HDMI) driver
5 * Copyright (C) 2013-2015 Mentor Graphics Inc.
6 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
21 #include <linux/dma-mapping.h>
24 #include <media/cec-notifier.h>
26 #include <linux/media-bus-format.h>
40 #include "dw-hdmi-audio.h"
41 #include "dw-hdmi-cec.h"
42 #include "dw-hdmi.h"
[all …]
/linux/drivers/net/phy/
H A Dsmsc.c1 // SPDX-License-Identifier: GPL-2.0+
3 * drivers/net/phy/smsc.c
21 #include <linux/phy.h>
27 /* Vendor-specific PHY Definitions */
70 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in smsc_phy_config_intr()
91 struct smsc_phy_priv *priv = phydev->priv; in smsc_phy_config_edpd()
93 if (priv->edpd_enable) in smsc_phy_config_edpd()
107 if (irq_status != -ENODEV) in smsc_phy_handle_interrupt()
124 struct smsc_phy_priv *priv = phydev->priv; in smsc_phy_config_init()
130 if (!priv->edpd_mode_set_by_user && phydev->irq != PHY_POLL) in smsc_phy_config_init()
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