| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | smsc911x.txt | 1 * Smart Mixed-Signal Connectivity (SMSC) LAN911x/912x Controller
4 - compatible : Should be "smsc,lan<model>", "smsc,lan9115"
5 - reg : Address and length of the io space for SMSC LAN
6 - interrupts : one or two interrupt specifiers
7 - The first interrupt is the SMSC LAN interrupt line
8 - The second interrupt (if present) is the PME (power
11 - phy-mode : See ethernet.txt file in the same directory
14 - reg-shift : Specify the quantity to shift the register offsets by
15 - reg-io-width : Specify the size (in bytes) of the IO accesses that
18 - smsc,irq-active-high : Indicates the IRQ polarity is active-high
[all …]
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| H A D | smsc,lan9115.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Smart Mixed-Signal Connectivity (SMSC) LAN911x/912x Controller
10 - Shawn Guo <shawnguo@kernel.org>
13 - $ref: ethernet-controller.yaml#
18 - const: smsc,lan9115
19 - items:
20 - enum:
21 - smsc,lan89218
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/phy/ |
| H A D | mediatek,tphy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/mediatek,tphy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek T-PHY Controller
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 The T-PHY controller supports physical layer functionality for a number of
17 Layout differences of banks between T-PHY V1 (mt8173/mt2701) and
18 T-PHY V2 (mt2712) / V3 (mt8195) when works on USB mode:
19 -----------------------------------
[all …]
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| /freebsd/sys/dev/mii/ |
| H A D | nsphyterreg.h | 3 /*-
4 * SPDX-License-Identifier: BSD-2-Clause
39 * DP83843 registers; We also have the MacPHYTER (DP83815) internal
40 * PHY register definitions here, since the two are, for our purposes,
44 #define MII_NSPHYTER_PHYSTS 0x10 /* PHY status */
65 #define PHYSTS_MP_DESCRLK 0x0200 /* de-scrambler lock */
72 #define MII_NSPHYTER_MIPSCR 0x11 /* MII interrupt PHY specific
78 #define MII_NSPHYTER_MIPGSR 0x12 /* MII interrupt PHY generic
85 #define MIPGSR_MSK_ANC 0x0800 /* mask auto-neg complete event */
96 #define PCSR_SINGLE_SD 0x8000 /* single-ended SD mode */
[all …]
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| /freebsd/sys/dev/ixgbe/ |
| H A D | ixgbe_x550.c | 3 Copyright (c) 2001-2020, Intel Corporation
47 * ixgbe_init_ops_X550 - Inits func ptrs and MAC type
55 struct ixgbe_mac_info *mac = &hw->mac; in ixgbe_init_ops_X550()
56 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; in ixgbe_init_ops_X550()
62 mac->ops.dmac_config = ixgbe_dmac_config_X550; in ixgbe_init_ops_X550()
63 mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550; in ixgbe_init_ops_X550()
64 mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550; in ixgbe_init_ops_X550()
65 mac->ops.setup_eee = NULL; in ixgbe_init_ops_X550()
66 mac->ops.set_source_address_pruning = in ixgbe_init_ops_X550()
68 mac->ops.set_ethertype_anti_spoofing = in ixgbe_init_ops_X550()
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| /freebsd/share/man/man4/ |
| H A D | sk.4 | 15 .\" 4. Neither the name of the author nor the names of any co-contributors
36 .Nd "SysKonnect SK-984x and SK-982x PCI Gigabit Ethernet adapter driver"
41 .Bd -ragged -offset indent
49 .Bd -literal -offset indent
55 driver provides support for the SysKonnect SK-984x and SK-982x series PCI
61 XMAC provides the gigabit MAC and PHY support while the GEnesis
65 allowing dual-port NIC configurations.
67 The SK-982x 1000baseT adapters also include a Broadcom BCM5400 1000baseTX
68 PHY which is used in place of the XMAC's internal PHY.
69 The Broadcom PHY is connected to the XMAC via its GMII port.
[all …]
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| H A D | sis.4 | 15 .\" 4. Neither the name of the author nor the names of any co-contributors
41 .Bd -ragged -offset indent
49 .Bd -literal -offset indent
63 The SiS 900 is a 100Mbps Ethernet MAC and MII-compliant transceiver
68 that it has no internal PHY, requiring instead an external transceiver
70 The SiS 900 and SiS 7016 both have a 128-bit multicast hash filter
73 The NS DP83815 is also a 100Mbps Ethernet MAC with integrated PHY.
81 .Bl -tag -width 10baseTXUTP
93 .Sq full-duplex
95 .Sq half-duplex
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| H A D | rl.4 | 15 .\" 4. Neither the name of the author nor the names of any co-contributors
41 .Bd -ragged -offset indent
49 .Bd -literal -offset indent
60 descriptor-based data transfer mechanism.
70 The 8129 differs from the 8139 in that the 8139 has an internal
72 whereas the 8129 uses an external PHY via an MII bus.
85 .Bl -tag -width xxxxxxxxxxxxxxxxxxxx
89 supported if the PHY chip attached to the RealTek controller
100 .Ar full-duplex
102 .Ar half-duplex
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| /freebsd/sys/contrib/device-tree/src/arm64/marvell/ |
| H A D | cn9130-cf-pro.dts | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2024 Josua Mayer <josua@solid-run.com>
9 /dts-v1/;
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/leds/common.h>
15 #include "cn9130-sr-som.dtsi"
16 #include "cn9130-cf.dtsi"
20 compatible = "solidrun,cn9130-clearfog-pro",
21 "solidrun,cn9130-sr-som", "marvell,cn9130";
23 gpio-keys {
[all …]
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| /freebsd/sys/contrib/device-tree/src/arm/samsung/ |
| H A D | s3c6410-smdk6410.dts | 1 // SPDX-License-Identifier: GPL-2.0
11 /dts-v1/;
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
31 fin_pll: oscillator-0 {
32 compatible = "fixed-clock";
33 clock-frequency = <12000000>;
34 clock-output-names = "fin_pll";
35 #clock-cells = <0>;
38 xusbxti: oscillator-1 {
[all …]
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| H A D | exynos5410-smdk5410.dts | 1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/irq.h>
27 stdout-path = "serial2:115200n8";
31 compatible = "fixed-clock";
32 clock-frequency = <24000000>;
33 clock-output-names = "fin_pll";
34 #clock-cells = <0>;
37 pmic_ap_clk: pmic-ap-clk {
39 compatible = "fixed-clock";
[all …]
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| /freebsd/sys/dev/le/ |
| H A D | lancereg.h | 3 /*-
4 * SPDX-License-Identifier: BSD-2-Clause
34 /*-
70 * - Am7990 Local Area Network Controller for Ethernet (LANCE)
71 * (and its descendent Am79c90 C-LANCE).
73 * - Am79c900 Integrated Local Area Communications Controller (ILACC)
75 * - Am79c960 PCnet-ISA Single-Chip Ethernet Controller for ISA
77 * - Am79c961 PCnet-ISA+ Jumperless Single-Chip Ethernet Controller
80 * - Am79c961A PCnet-ISA II Jumperless Full-Duplex Single-Chip
83 * - Am79c965A PCnet-32 Single-Chip 32-bit Ethernet Controller
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/memory-controllers/ |
| H A D | exynos-srom.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/exynos-srom.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
19 - const: samsung,exynos4210-srom
24 "#address-cells":
27 "#size-cells":
35 <bank-number> 0 <parent address of bank> <size>
39 "^.*@[0-3],[a-f0-9]+$":
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| /freebsd/sys/contrib/device-tree/Bindings/mmc/ |
| H A D | arasan,sdhci.txt | 3 The bindings follow the mmc[1], clock[2], interrupt[3] and phy[4] bindings.
7 [2] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 [3] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
9 [4] Documentation/devicetree/bindings/phy/phy-bindings.txt
12 - compatible: Compatibility string. One of:
13 - "arasan,sdhci-8.9a": generic Arasan SDHCI 8.9a PHY
14 - "arasan,sdhci-4.9a": generic Arasan SDHCI 4.9a PHY
15 - "arasan,sdhci-5.1": generic Arasan SDHCI 5.1 PHY
16 - "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1": rk3399 eMMC PHY
17 For this device it is strongly suggested to include arasan,soc-ctl-syscon.
[all …]
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| H A D | arasan,sdhci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
[all...] |
| /freebsd/sys/dev/e1000/ |
| H A D | e1000_mac.c | 2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
42 * e1000_init_mac_ops_generic - Initialize MAC function pointers
45 * Setups up the function pointers to no-op functions
49 struct e1000_mac_info *mac = &hw->mac; in e1000_init_mac_ops_generic()
53 mac->ops.init_params = e1000_null_ops_generic; in e1000_init_mac_ops_generic()
54 mac->ops.init_hw = e1000_null_ops_generic; in e1000_init_mac_ops_generic()
55 mac->ops.reset_hw = e1000_null_ops_generic; in e1000_init_mac_ops_generic()
56 mac->ops.setup_physical_interface = e1000_null_ops_generic; in e1000_init_mac_ops_generic()
57 mac->ops.get_bus_info = e1000_null_ops_generic; in e1000_init_mac_ops_generic()
[all …]
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| /freebsd/sys/dev/usb/net/ |
| H A D | if_udav.c | 3 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
17 * 3. Neither the name of the author nor the names of any co-contributors
36 * DM9601(DAVICOM USB to Ethernet MAC Controller with Integrated 10/100 PHY)
38 * http://ptm2.cc.utu.fi/ftp/network/cards/DM9601/From_NET/DM9601-DS-P01-930914.pdf
175 /* Corega USB-TXC */
239 udav_csr_read(sc, UDAV_PAR, ue->ue_eaddr, ETHER_ADDR_LEN); in udav_attach_post()
247 if (uaa->usb_mode != USB_MODE_HOST) in udav_probe()
249 if (uaa->info.bConfigIndex != UDAV_CONFIG_INDEX) in udav_probe()
251 if (uaa->info.bIfaceIndex != UDAV_IFACE_INDEX) in udav_probe()
[all …]
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| /freebsd/sys/dev/isci/ |
| H A D | isci_controller.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
6 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
99 isci_controller->is_started = TRUE; in scif_cb_controller_start_complete()
101 /* Set bits for all domains. We will clear them one-by-one once in scif_cb_controller_start_complete()
106 isci_controller->initial_discovery_mask = (1 << SCI_MAX_DOMAINS) - 1; in scif_cb_controller_start_complete()
111 isci_controller->domain[index].sci_object; in scif_cb_controller_start_complete()
122 isci_controller, &isci_controller->domain[index]); in scif_cb_controller_start_complete()
148 isci_controller->is_started = FALSE; in scif_cb_controller_stop_complete()
183 if (!sci_pool_empty(isci_controller->unmap_buffer_pool)) { in scif_cb_controller_allocate_memory()
[all …]
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| /freebsd/sys/contrib/device-tree/src/arm/st/ |
| H A D | stm32mp157c-lxa-mc1.dts | 1 /* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) */
3 * Copyright (C) 2020 STMicroelectronics - All Rights Reserved
7 /dts-v1/;
10 #include "stm32mp15xx-osd32.dtsi"
11 #include "stm32mp15xxac-pinctrl.dtsi"
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/pwm/pwm.h>
17 model = "Linux Automation MC-1 board";
18 compatible = "lxa,stm32mp157c-mc1", "oct,stm32mp15xx-osd32", "st,stm32mp157";
28 compatible = "pwm-backlight";
[all …]
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| /freebsd/sys/dev/etherswitch/arswitch/ |
| H A D | arswitch_8316.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2011-2012 Stefan Bethke.
77 * + Port 4 is either connected to the CPU or to the internal switch. in ar8316_hw_setup()
79 if (sc->is_rgmii && sc->phy4cpu) { in ar8316_hw_setup()
80 arswitch_writereg(sc->sc_dev, AR8X16_REG_MODE, in ar8316_hw_setup()
82 device_printf(sc->sc_dev, in ar8316_hw_setup()
83 "%s: MAC port == RGMII, port 4 = dedicated PHY\n", in ar8316_hw_setup()
85 } else if (sc->is_rgmii) { in ar8316_hw_setup()
86 arswitch_writereg(sc->sc_dev, AR8X16_REG_MODE, in ar8316_hw_setup()
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| /freebsd/sys/contrib/device-tree/src/arm/ti/omap/ |
| H A D | omap3-lilly-dbb056.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 /dts-v1/;
7 #include "omap3-lilly-a83x.dtsi"
10 model = "INCOstartec LILLY-DBB056 (DM3730)";
11 …compatible = "incostartec,omap3-lilly-dbb056", "incostartec,omap3-lilly-a83x", "ti,omap3630", "ti,…
15 vaux2: regulator-vaux2 {
16 compatible = "ti,twl4030-vaux2";
17 regulator-min-microvolt = <2800000>;
18 regulator-max-microvolt = <2800000>;
19 regulator-always-on;
[all …]
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| /freebsd/sys/dev/etherswitch/ar40xx/ |
| H A D | ar40xx_hw_psgmii.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
76 * Routines that control the ess-psgmii block - the interconnect
77 * between the ess-switch and the external multi-port PHY
85 bus_space_write_4(sc->sc_psgmii_mem_tag, sc->sc_psgmii_mem_handle, in ar40xx_hw_psgmii_reg_write()
87 bus_space_barrier(sc->sc_psgmii_mem_tag, sc->sc_psgmii_mem_handle, in ar40xx_hw_psgmii_reg_write()
88 0, sc->sc_psgmii_mem_size, BUS_SPACE_BARRIER_WRITE); in ar40xx_hw_psgmii_reg_write()
96 bus_space_barrier(sc->sc_psgmii_mem_tag, sc->sc_psgmii_mem_handle, in ar40xx_hw_psgmii_reg_read()
97 0, sc->sc_psgmii_mem_size, BUS_SPACE_BARRIER_READ); in ar40xx_hw_psgmii_reg_read()
98 ret = bus_space_read_4(sc->sc_psgmii_mem_tag, sc->sc_psgmii_mem_handle, in ar40xx_hw_psgmii_reg_read()
[all …]
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| /freebsd/sys/dev/msk/ |
| H A D | if_mskreg.h | 17 * are provided to you under the BSD-type license terms provided
22 * - Redistributions of source code must retain the above copyright
24 * - Redistributions in binary form must reproduce the above
28 * - Neither the name of Marvell nor the names of its contributors
48 /*-
49 * SPDX-License-Identifier: BSD-4-Clause AND BSD-3-Clause
65 * 4. Neither the name of the author nor the names of any co-contributors
82 /*-
110 * D-Link PCI vendor ID
154 * D-Link gigabit ethernet device ID
[all …]
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| /freebsd/sys/dev/vge/ |
| H A D | if_vgereg.h | 1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
18 * 4. Neither the name of the author nor the names of any co-contributors
37 * Definitions for the built-in copper PHY can be found in vgphy.h.
41 * using 32-bit I/O cycles, but some of them are less than 32 bits
114 #define VGE_PHYSTS0 0x6E /* PHY status register */
115 #define VGE_PHYSTS1 0x6F /* PHY status register */
119 #define VGE_SSTIMER 0x74 /* single-shot timer */
233 #define VGE_CR3_INT_SWPEND 0x01 /* disable multi-level int bits */
238 #define VGE_CR3_STOP_FORCE 0x40 /* force NIC to stopped state */
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| /freebsd/sys/contrib/alpine-hal/ |
| H A D | al_hal_nb_regs.h | 1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
64 /* [0x8] Force init reset. */
66 /* [0xc] Force init reset per DECEI mode. */
101 /* [0x6c] Read-only that reflects CPU Cluster Local GIC base high address */
103 /* [0x70] Read-only that reflects CPU Cluster Local GIC base low address */
105 /* [0x74] Read-only that reflects the device's IOGIC base high address. */
107 /* [0x78] Read-only that reflects IOGIC base low address */
463 /* Defines the internal CPU GIC operating frequency ratio with the main CPU clock.
480 /* Value read in the Cluster ID Affinity Level-1 field, bits[15:8], of the Multiprocessor Affinity
[all …]
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