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/linux/Documentation/networking/device_drivers/ethernet/davicom/
H A Ddm9000.rst1 .. SPDX-License-Identifier: GPL-2.0
9 Ben Dooks <ben@simtec.co.uk> <ben-linux@fluff.org>
13 ------------
15 This file describes how to use the DM9000 platform-device based network driver
25 ----------------------------
37 An example from arch/arm/mach-s3c/mach-bast.c is::
91 -------------
94 device, whether or not an external PHY is attached to the device and
95 the availability of an external configuration EEPROM.
113 The chip is connected to an external PHY.
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Dphy-miphy28lp.txt1 STMicroelectronics STi MIPHY28LP PHY binding
4 This binding describes a miphy device that is used to control PHY hardware
8 - compatible : Should be "st,miphy28lp-phy".
9 - st,syscfg : Should be a phandle of the system configuration register group
12 Required nodes : A sub-node is required for each channel the controller
14 'reg' and 'reg-names' properties are used inside these
19 - #phy-cells : Should be 1 (See second example)
21 - PHY_TYPE_SATA
22 - PHY_TYPE_PCI
23 - PHY_TYPE_USB3
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/linux/arch/arm64/boot/dts/marvell/
H A Dcn9130-cf-pro.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2024 Josua Mayer <josua@solid-run.com>
9 /dts-v1/;
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/leds/common.h>
15 #include "cn9130-sr-som.dtsi"
16 #include "cn9130-cf.dtsi"
20 compatible = "solidrun,cn9130-clearfog-pro",
21 "solidrun,cn9130-sr-som", "marvell,cn9130";
23 gpio-keys {
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/linux/drivers/net/ethernet/davicom/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
31 bool "Force simple NSR based PHY polling"
36 costly MII PHY reads. Note, this will not work if the chip is
37 operating with an external PHY.
/linux/arch/mips/include/asm/mach-bcm63xx/
H A Dbcm63xx_dev_enet.h1 /* SPDX-License-Identifier: GPL-2.0 */
21 /* or fill phy info to use an external one */
26 /* if has_phy, use autonegotiated pause parameters or force
68 #define ENETSW_PORTS_6328 5 /* 4 FE PHY + 1 RGMII */
69 #define ENETSW_PORTS_6368 6 /* 4 FE PHY + 2 RGMII */
/linux/drivers/ata/
H A Dahci.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * ahci.h - Common AHCI SATA definitions and declarations
6 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2004-2005 Red Hat, Inc.
12 * as Documentation/driver-api/libata.rst
25 #include <linux/phy/phy.h>
80 HOST_RESET = BIT(0), /* reset controller; self-clear */
86 HOST_CAP_SXS = BIT(5), /* Supports External SATA */
92 HOST_CAP_FBS = BIT(16), /* FIS-based switching support */
98 HOST_CAP_SSS = BIT(27), /* Staggered Spin-up */
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/linux/drivers/net/ethernet/sun/
H A Dsunhme.h1 /* SPDX-License-Identifier: GPL-2.0 */
38 #define GREG_STAT_ACNTEXP 0x00000004 /* Align-error counter expired */
39 #define GREG_STAT_CCNTEXP 0x00000008 /* CRC-error counter expired */
40 #define GREG_STAT_LCNTEXP 0x00000010 /* Length-error counter expired */
42 #define GREG_STAT_CVCNTEXP 0x00000040 /* Code-violation counter expired */
46 #define GREG_STAT_MAXPKTERR 0x00000400 /* Max-packet size error */
47 #define GREG_STAT_NCNTEXP 0x00000800 /* Normal-collision counter expired */
48 #define GREG_STAT_ECNTEXP 0x00001000 /* Excess-collision counter expired */
49 #define GREG_STAT_LCCNTEXP 0x00002000 /* Late-collision counter expired */
50 #define GREG_STAT_FCNTEXP 0x00004000 /* First-collision counter expired */
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H A Dsunhme.c1 // SPDX-License-Identifier: GPL-2.0
10 * 2000/11/11 Willy Tarreau <willy AT meta-x.org>
11 * - port to non-sparc architectures. Tested only on x86 and
13 * - ability to specify the MAC address at module load time by passing this
20 #include <linux/dma-mapping.h>
83 /* "Auto Switch Debug" aka phy debug */
111 tlp->tstamp = (unsigned int)jiffies;
112 tlp->tx_new = hp->tx_new;
113 tlp->tx_old = hp->tx_old;
114 tlp->action = a;
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/linux/drivers/net/dsa/realtek/
H A Drtl8365mb.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Realtek SMI subdriver for the Realtek RTL8365MB-VC ethernet switch.
4 * Copyright (C) 2021 Alvin Šipraga <alsi@bang-olufsen.dk>
5 * Copyright (C) 2021 Michael Rasmussen <mir@bang-olufsen.dk>
7 * The RTL8365MB-VC is a 4+1 port 10/100/1000M switch controller. It includes 4
9 * can be connected to the CPU - or another PHY - vi
659 rtl8365mb_phy_ocp_prepare(struct realtek_priv * priv,int phy,u32 ocp_addr) rtl8365mb_phy_ocp_prepare() argument
689 rtl8365mb_phy_ocp_read(struct realtek_priv * priv,int phy,u32 ocp_addr,u16 * data) rtl8365mb_phy_ocp_read() argument
733 rtl8365mb_phy_ocp_write(struct realtek_priv * priv,int phy,u32 ocp_addr,u16 data) rtl8365mb_phy_ocp_write() argument
775 rtl8365mb_phy_read(struct realtek_priv * priv,int phy,int regnum) rtl8365mb_phy_read() argument
803 rtl8365mb_phy_write(struct realtek_priv * priv,int phy,int regnum,u16 val) rtl8365mb_phy_write() argument
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/linux/drivers/net/ethernet/intel/igb/
H A De1000_defines.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
62 /* Interrupt acknowledge Auto-mask */
118 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
119 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
123 #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
184 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
185 #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
186 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
188 #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
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/linux/drivers/phy/
H A Dphy-xgene.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AppliedMicro X-Gene Multi-purpose PHY driver
10 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
12 * PLL clock macro is used to generate the clock for the PHY. This driver
13 * configures the first PLL CMU, the second PLL CMU, and programs the PHY to
19 * -----------------
20 * | Internal | |------|
21 * | Ref PLL CMU |----| | ------------- ---------
22 * ------------ ---- | MUX |-----|PHY PLL CMU|----| Serdes|
23 * | | | | ---------
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/linux/drivers/net/dsa/mv88e6xxx/
H A Dglobal2.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
21 return mv88e6xxx_read(chip, chip->info->global2_addr, reg, val); in mv88e6xxx_g2_read()
26 return mv88e6xxx_write(chip, chip->info->global2_addr, reg, val); in mv88e6xxx_g2_write()
32 return mv88e6xxx_wait_bit(chip, chip->info->global2_addr, reg, in mv88e6xxx_g2_wait_bit()
146 const u16 port_mask = BIT(mv88e6xxx_num_ports(chip)) - 1; in mv88e6xxx_g2_trunk_mapping_write()
155 const u16 port_mask = BIT(mv88e6xxx_num_ports(chip)) - 1; in mv88e6xxx_g2_trunk_clear()
212 /* Offset 0x0B: Cross-chip Port VLAN (Addr) Register
213 * Offset 0x0C: Cross-chip Port VLAN Data Register
228 /* 9-bit Cross-chip PVT pointer: with MV88E6XXX_G2_MISC_5_BIT_PORT in mv88e6xxx_g2_pvt_op()
[all …]
/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_top.h1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
31 * struct split_pipe_cfg - pipe configuration for dual display panels
56 * struct dpu_vsync_source_cfg - configure vsync source and configure the
78 * struct dpu_hw_mdp_ops - interface to the MDP TOP Hw driver functions
102 * setup_clk_force_ctrl - set clock force control
105 * @enable: force on enable
106 * @return: if the clock is forced-on by this function
112 * get_danger_status - get danger status
120 * setup_vsync_source - setup vsync source configuration details
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/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_link.c1 /* Copyright 2008-2013 Broadcom Corporation
8 * at http://www.gnu.org/licenses/gpl-2.0.html (the "GPL").
32 typedef int (*read_sfp_module_eeprom_func_p)(struct bnx2x_phy *phy,
43 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1)
205 (_phy)->def_md_devad, \
211 (_phy)->def_md_devad, \
217 static int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
239 * bnx2x_check_lfa - This function checks if link reinitialization is required,
251 struct bnx2x *bp = params->bp; in bnx2x_check_lfa()
254 REG_RD(bp, params->lfa_base + in bnx2x_check_lfa()
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/linux/drivers/phy/allwinner/
H A Dphy-sun4i-usb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Allwinner sun4i USB phy driver
5 * Copyright (C) 2014-2015 Hans de Goede <hdegoede@redhat.com>
18 #include <linux/extcon-provider.h>
26 #include <linux/phy/phy.h>
27 #include <linux/phy/phy-sun4i-usb.h>
57 /* sunxi has the phy id/vbus pins not connected, so we use the force bits */
69 /* Private Control Bits for Each PHY */
119 struct phy *phy; member
144 #define to_sun4i_usb_phy_data(phy) \ argument
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/linux/Documentation/networking/
H A Dsfp-phylink.rst1 .. SPDX-License-Identifier: GPL-2.0
10 phylink is a mechanism to support hot-pluggable networking modules
11 directly connected to a MAC without needing to re-initialise the
12 adapter on hot-plug events.
14 phylink supports conventional phylib-based setups, fixed link setups
23 1. PHY mode
25 In PHY mode, we use phylib to read the current link settings from
26 the PHY, and pass them to the MAC driver. We expect the MAC driver
32 Fixed mode is the same as PHY mode as far as the MAC driver is
35 3. In-band mode
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/linux/drivers/net/ethernet/intel/e1000e/
H A Ddefines.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
17 #define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */
37 #define E1000_CTRL_EXT_FORCE_SMBUS 0x00000800 /* Force SMBus mode */
46 #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
100 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
101 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
104 #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
183 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
184 #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
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/linux/arch/arm/boot/dts/st/
H A Dstm32mp157c-lxa-mc1.dts1 /* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) */
3 * Copyright (C) 2020 STMicroelectronics - All Rights Reserved
7 /dts-v1/;
10 #include "stm32mp15xx-osd32.dtsi"
11 #include "stm32mp15xxac-pinctrl.dtsi"
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/pwm/pwm.h>
17 model = "Linux Automation MC-1 board";
18 compatible = "lxa,stm32mp157c-mc1", "oct,stm32mp15xx-osd32", "st,stm32mp157";
28 compatible = "pwm-backlight";
[all …]
H A Dstm32mp153c-lxa-fairytux2.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
3 * Copyright (C) 2020 STMicroelectronics - All Rights Reserved
10 #include "stm32mp15xx-osd32.dtsi"
11 #include "stm32mp15xxac-pinctrl.dtsi"
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/input/input.h>
15 #include <dt-bindings/leds/common.h>
16 #include <dt-bindings/pwm/pwm.h>
31 stdout-path = &uart4;
35 compatible = "pwm-backlight";
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/linux/drivers/net/fddi/skfp/
H A Dpcmplc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
20 * The following external SMT functions are referenced :
26 * The following external HW dependent functions are referenced :
67 #define GO_STATE(x) (mib->fddiPORTPCMState = (x)|AFLAG)
68 #define ACTIONS_DONE() (mib->fddiPORTPCMState &= ~AFLAG)
109 * PCL-S control register
110 * this register in the PLC-S controls the scrambling parameters
121 * PCL-S control register
122 * this register in the PLC-S controls the scrambling parameters
133 * external vars
[all …]
/linux/drivers/net/ethernet/dec/tulip/
H A Ddmfe.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 DAVICOM Web-Site: www.davicom.com.tw
10 Author: Sten Wang, 886-3-5798797-8517, E-mail: sten_wang@davicom.com.tw
13 (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
22 Removed IRQ 0-15 assumption
69 #include <linux/dma-mapping.h>
91 /* Board/System/Debug information/definition ---------------- */
102 #define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
103 #define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
140 #define DMFE_TX_TIMEOUT ((3*HZ)/2) /* tx packet time-out time 1.5 s" */
[all …]
/linux/include/linux/ssb/
H A Dssb_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
19 #define SSB_EXTIF_BASE 0x1f000000U /* External Interface region base address */
33 #define SSB_MAX_NR_CORES ((SSB_ENUM_LIMIT - SSB_ENUM_BASE) / SSB_CORE_SIZE)
97 #define SSB_INTVEC_EXTIF 0x00000020 /* Enable interrupts for external i/f */
104 #define SSB_TMSLOW_FGC 0x00020000 /* Force Gated Clocks On */
108 #define SSB_TMSHIGH_SERR 0x00000001 /* S-error */
168 * in two-byte quantities.
192 #define SSB_SPROM1_ETHPHY 0x005A /* Ethernet PHY settings */
202 #define SSB_SPROM1_BINF_ANTBG 0x3000 /* Available B-PHY and G-PHY antennas */
204 #define SSB_SPROM1_BINF_ANTA 0xC000 /* Available A-PHY antennas */
[all …]
/linux/drivers/net/ethernet/intel/e1000/
H A De1000_hw.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2006 Intel Corporation. */
104 /* PHY status info structure and supporting enums */
280 /* PHY */
422 /* MAC decode size is 128K - This is the size of BAR0 */
443 (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
486 * E1000_RAR_ENTRIES - 1 multicast addresses.
503 /* Receive Descriptor - Extended */
529 /* Receive Descriptor - Packet Split */
553 __le16 length[3]; /* length of buffers 1-3 */
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3399-evb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include <dt-bindings/pwm/pwm.h>
8 #include "rk3399-base.dtsi"
12 compatible = "rockchip,rk3399-evb", "rockchip,rk3399";
20 compatible = "pwm-backlight";
21 brightness-levels = <
54 default-brightness-level = <200>;
58 edp_panel: edp-panel {
59 compatible = "lg,lp079qx1-sp0v";
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/linux/drivers/net/ethernet/natsemi/
H A Dnatsemi.c3 Written/copyright 1999-2001 by Donald Becker.
23 [link no longer provides useful info -jgarzik]
62 /* Updated to recommendations in pci-skeleton v2.03. */
64 /* The user-configurable values.
72 static int debug = -1;
76 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
80 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
101 There are no ill effects from too-large receive rings. */
121 * The nic writes 32-bit values, even if the upper bytes of
122 * a 32-bit value are beyond the end of the buffer.
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