xref: /linux/Documentation/devicetree/bindings/gpio/gpio-mmio.yaml (revision 6574f01ef95dd9029a0230f4f56a62f93fdd8319) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/gpio/gpio-mmio.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Generic MMIO GPIO
8
9maintainers:
10  - Linus Walleij <linusw@kernel.org>
11  - Bartosz Golaszewski <brgl@bgdev.pl>
12
13description:
14  Some simple GPIO controllers may consist of a single data register or a pair
15  of set/clear-bit registers. Such controllers are common for glue logic in
16  FPGAs or ASICs. Commonly, these controllers are accessed over memory-mapped
17  NAND-style parallel busses.
18
19properties:
20  compatible:
21    enum:
22      - brcm,bcm6345-gpio
23      - intel,ixp4xx-expansion-bus-mmio-gpio
24      - ni,169445-nand-gpio
25      - opencores,gpio
26      - wd,mbl-gpio # Western Digital MyBook Live memory-mapped GPIO controller
27
28  big-endian: true
29
30  '#gpio-cells':
31    const: 2
32
33  gpio-controller: true
34
35  little-endian: true
36
37  reg:
38    minItems: 1
39    description:
40      A list of registers in the controller. The width of each register is
41      determined by its size. All registers must have the same width. The number
42      of GPIOs is set by the width, with bit 0 corresponding to GPIO 0, unless
43      the ngpios property further restricts the number of used lines.
44    items:
45      - description:
46          Register to READ the value of the GPIO lines. If GPIO line is high,
47          the bit will be set. If the GPIO line is low, the bit will be cleared.
48          This register may also be used to drive GPIOs if the SET register is
49          omitted.
50      - description:
51          Register to SET the value of the GPIO lines. Setting a bit in this
52          register will drive the GPIO line high.
53      - description:
54          Register to CLEAR the value of the GPIO lines. Setting a bit in this
55          register will drive the GPIO line low. If this register is omitted,
56          the SET register will be used to clear the GPIO lines as well, by
57          actively writing the line with 0.
58      - description:
59          Register to set the line as OUTPUT. Setting a bit in this register
60          will turn that line into an output line. Conversely, clearing a bit
61          will turn that line into an input.
62      - description:
63          Register to set this line as INPUT. Setting a bit in this register
64          will turn that line into an input line. Conversely, clearing a bit
65          will turn that line into an output.
66
67  reg-names:
68    minItems: 1
69    maxItems: 5
70    items:
71      enum:
72        - dat
73        - set
74        - clr
75        - dirout
76        - dirin
77
78  native-endian: true
79
80  ngpios:
81    minimum: 1
82    maximum: 63
83    description:
84      If this property is present the number of usable GPIO lines are restricted
85      to the first 0 .. ngpios lines. This is useful when the GPIO MMIO register
86      has 32 bits for GPIO but only the first 12 are actually connected to
87      real electronics, and then we set ngpios to 12.
88
89  no-output:
90    $ref: /schemas/types.yaml#/definitions/flag
91    description:
92      If this property is present, the controller cannot drive the GPIO lines.
93
94if:
95  properties:
96    compatible:
97      contains:
98        const: intel,ixp4xx-expansion-bus-mmio-gpio
99then:
100  $ref: /schemas/memory-controllers/intel,ixp4xx-expansion-peripheral-props.yaml#
101
102patternProperties:
103  "^.+-hog(-[0-9]+)?$":
104    type: object
105    required:
106      - gpio-hog
107
108required:
109  - compatible
110  - reg
111  - reg-names
112  - '#gpio-cells'
113  - gpio-controller
114
115unevaluatedProperties: false
116
117examples:
118  - |
119    gpio@1f300010 {
120      compatible = "ni,169445-nand-gpio";
121      reg = <0x1f300010 0x4>;
122      reg-names = "dat";
123      gpio-controller;
124      #gpio-cells = <2>;
125    };
126
127    gpio@e0100000 {
128      compatible = "wd,mbl-gpio";
129      reg-names = "dat";
130      reg = <0xe0100000 0x1>;
131      #gpio-cells = <2>;
132      gpio-controller;
133      no-output;
134    };
135
136    gpio@fffe0406 {
137      compatible = "brcm,bcm6345-gpio";
138      reg-names = "dirout", "dat";
139      reg = <0xfffe0406 2>, <0xfffe040a 2>;
140      ngpios = <15>;
141      native-endian;
142      gpio-controller;
143      #gpio-cells = <2>;
144    };
145
146    bus@c4000000 {
147        compatible = "intel,ixp42x-expansion-bus-controller", "syscon";
148        reg = <0xc4000000 0x30>;
149        native-endian;
150        #address-cells = <2>;
151        #size-cells = <1>;
152        ranges = <0 0x0 0x50000000 0x01000000>;
153        dma-ranges = <0 0x0 0x50000000 0x01000000>;
154        gpio@1,0 {
155            compatible = "intel,ixp4xx-expansion-bus-mmio-gpio";
156            gpio-controller;
157            #gpio-cells = <2>;
158            big-endian;
159            reg = <1 0x00000000 0x2>;
160            reg-names = "dat";
161            intel,ixp4xx-eb-write-enable = <1>;
162        };
163    };
164