xref: /linux/Documentation/devicetree/bindings/perf/amlogic,g12-ddr-pmu.yaml (revision cdd5b5a9761fd66d17586e4f4ba6588c70e640ea) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/perf/amlogic,g12-ddr-pmu.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Amlogic G12 DDR performance monitor
8
9maintainers:
10  - Jiucheng Xu <jiucheng.xu@amlogic.com>
11
12description: |
13  Amlogic G12 series SoC integrate DDR bandwidth monitor.
14  A timer is inside and can generate interrupt when timeout.
15  The bandwidth is counted in the timer ISR. Different platform
16  has different subset of event format attribute.
17
18properties:
19  compatible:
20    enum:
21      - amlogic,g12a-ddr-pmu
22      - amlogic,g12b-ddr-pmu
23      - amlogic,sm1-ddr-pmu
24
25  reg:
26    items:
27      - description: DMC bandwidth register space.
28      - description: DMC PLL register space.
29
30  interrupts:
31    items:
32      - description: The IRQ of the inside timer timeout.
33
34required:
35  - compatible
36  - reg
37  - interrupts
38
39additionalProperties: false
40
41examples:
42  - |
43    #include <dt-bindings/interrupt-controller/arm-gic.h>
44    pmu {
45        #address-cells = <2>;
46        #size-cells = <2>;
47
48        pmu@ff638000 {
49            compatible = "amlogic,g12a-ddr-pmu";
50            reg = <0x0 0xff638000 0x0 0x100>,
51                  <0x0 0xff638c00 0x0 0x100>;
52            interrupts = <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>;
53        };
54    };
55