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/freebsd/sys/riscv/vmm/
H A Dvmm_fence.c49 struct vmm_fence *fence; in vmm_fence_dequeue() local
53 fence = &queue[hypctx->fence_queue_head]; in vmm_fence_dequeue()
54 if (fence->type != VMM_RISCV_FENCE_INVALID) { in vmm_fence_dequeue()
55 *new_fence = *fence; in vmm_fence_dequeue()
56 fence->type = VMM_RISCV_FENCE_INVALID; in vmm_fence_dequeue()
72 struct vmm_fence *fence; in vmm_fence_enqueue() local
76 fence = &queue[hypctx->fence_queue_tail]; in vmm_fence_enqueue()
77 if (fence->type == VMM_RISCV_FENCE_INVALID) { in vmm_fence_enqueue()
78 *fence = *new_fence; in vmm_fence_enqueue()
91 vmm_fence_process_one(struct vmm_fence *fence) in vmm_fence_process_one() argument
[all …]
H A Dvmm_sbi.c45 struct vmm_fence fence; in vmm_sbi_handle_rfnc() local
61 fence.start = hypctx->guest_regs.hyp_a[2]; in vmm_sbi_handle_rfnc()
62 fence.size = hypctx->guest_regs.hyp_a[3]; in vmm_sbi_handle_rfnc()
63 fence.asid = hypctx->guest_regs.hyp_a[4]; in vmm_sbi_handle_rfnc()
67 fence.type = VMM_RISCV_FENCE_I; in vmm_sbi_handle_rfnc()
70 fence.type = VMM_RISCV_FENCE_VMA; in vmm_sbi_handle_rfnc()
73 fence.type = VMM_RISCV_FENCE_VMA_ASID; in vmm_sbi_handle_rfnc()
106 vmm_fence_add(hyp->vm, &cpus, &fence); in vmm_sbi_handle_rfnc()
H A Dvmm_fence.h41 void vmm_fence_add(struct vm *vm, cpuset_t *cpus, struct vmm_fence *fence);
/freebsd/sys/riscv/include/
H A Datomic.h40 #define fence() __asm __volatile("fence" ::: "memory"); macro
41 #define mb() fence()
42 #define rmb() fence()
43 #define wmb() fence()
56 fence(); \
62 fence(); \
74 fence(); \
82 fence(); \
94 fence(); \
102 fence(); \
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H A Dcpufunc.h84 /* NB: fence() is defined as a macro in <machine/atomic.h>. */
90 __asm __volatile("fence.i" ::: "memory"); in fence_i()
/freebsd/share/man/man9/
H A Datomic.9272 .Ss Thread Fence Operations
273 Alternatively, a programmer can use atomic thread fence operations to
278 When a fence has acquire semantics, all prior loads (by program order) must
280 Thus, an acquire fence is a two-way barrier for load operations.
286 When a fence has release semantics, all prior loads or stores (by program
289 Thus, a release fence is a two-way barrier for store operations.
298 For example, a store prior to the fence (in program order) may be completed
299 after a load subsequent to the fence.
305 In C11, a release fence by one thread synchronizes with an acquire fence by
306 another thread when an atomic load that is prior to the acquire fence (by
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H A Drefcount.9178 unconditionally executes a release fence (see
180 synchronizes with an acquire fence executed right before
/freebsd/contrib/jemalloc/include/jemalloc/internal/
H A Datomic_gcc_sync.h51 * 1. store() is weak-fence -> store -> strong fence, load() is load ->
52 * strong-fence.
53 * 2. store() is strong-fence -> store, load() is strong-fence -> load ->
54 * weak-fence.
59 * fence after seq_cst stores, and have naked loads. So we want the strong
/freebsd/sys/dev/hyperv/vmbus/amd64/
H A Dhyperv_machdep.c137 #define HYPERV_TSC_TIMECOUNT(fence) \ argument
139 hyperv_tc64_tsc_##fence(void) \
149 fence(); \
169 hyperv_tsc_timecount_##fence(struct timecounter *tc __unused) \
172 return (hyperv_tc64_tsc_##fence()); \
/freebsd/share/man/man3/
H A DATOMIC_VAR_INIT.3245 Acquire fence.
247 Release fence.
249 Acquire and release fence.
251 Sequentially consistent acquire and release fence.
/freebsd/sys/dev/ioat/
H A Dioat_internal.h129 uint32_t fence:1; member
162 uint32_t fence:1; member
193 uint32_t fence:1; member
221 uint32_t fence:1; member
300 uint32_t fence:1; member
338 uint32_t fence:1; member
380 uint32_t fence:1; member
/freebsd/contrib/llvm-project/compiler-rt/lib/xray/
H A Dxray_fdr_log_writer.h84 // We need this atomic fence here to ensure that other threads attempting to
114 // We need this atomic fence here to ensure that other threads attempting to
158 // We need this atomic fence here to ensure that other threads attempting to
183 // We need this atomic fence here to ensure that other threads attempting to
206 // We need this atomic fence here to ensure that other threads attempting to
/freebsd/contrib/ofed/include/
H A Dudma_barrier.h75 This is required to fence writes created by the libibverbs user. Those
110 #define udma_to_device_barrier() fence()
148 #define udma_from_device_barrier() fence()
162 Compared to udma_to_device_barrier() this barrier is not required to fence
218 #define mmio_flush_writes() fence()
/freebsd/sys/dev/bnxt/bnxt_re/
H A Dib_verbs.c536 struct bnxt_re_legacy_fence_data *fence = &pd->fence; in bnxt_re_legacy_create_fence_wqe() local
537 struct ib_mr *ib_mr = &fence->mr->ib_mr; in bnxt_re_legacy_create_fence_wqe()
538 struct bnxt_qplib_swqe *wqe = &fence->bind_wqe; in bnxt_re_legacy_create_fence_wqe()
551 wqe->bind.va = (u64)fence->va; in bnxt_re_legacy_create_fence_wqe()
552 wqe->bind.length = fence->size; in bnxt_re_legacy_create_fence_wqe()
556 /* Save the initial rkey in fence structure for now; in bnxt_re_legacy_create_fence_wqe()
559 fence->bind_rkey = ib_inc_rkey(fence->mw->rkey); in bnxt_re_legacy_create_fence_wqe()
568 struct bnxt_re_legacy_fence_data *fence = &pd->fence; in bnxt_re_legacy_bind_fence_mw() local
569 struct bnxt_qplib_swqe *fence_wqe = &fence->bind_wqe; in bnxt_re_legacy_bind_fence_mw()
573 /* TODO: Need SQ locking here when Fence WQE in bnxt_re_legacy_bind_fence_mw()
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/freebsd/contrib/mandoc/
H A Deqn.h61 char *left; /* Left-hand fence. */
62 char *right; /* Right-hand fence. */
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelDAGToDAG.cpp143 MachineSDNode *Fence = nullptr; in Select() local
146 // We lower a single-thread fence to a pseudo compiler barrier instruction in Select()
149 Fence = CurDAG->getMachineNode(WebAssembly::COMPILER_FENCE, in Select()
158 Fence = CurDAG->getMachineNode( in Select()
170 ReplaceNode(Node, Fence); in Select()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVInstructionSelector.cpp1277 // The only fence that needs an instruction is a sequentially-consistent in emitFence()
1278 // cross-thread fence. in emitFence()
1281 // fence rw, rw in emitFence()
1282 MIB.buildInstr(RISCV::FENCE, {}, {}) in emitFence()
1308 // fence acq_rel -> fence.tso in emitFence()
1312 // fence acquire -> fence r, rw in emitFence()
1317 // fence release -> fence rw, w in emitFence()
1322 // fence seq_cst -> fence rw, rw in emitFence()
1327 MIB.buildInstr(RISCV::FENCE, {}, {}).addImm(Pred).addImm(Succ); in emitFence()
/freebsd/stand/efi/include/arm/
H A Defibind.h77 // Memory Fence forces serialization, and is needed to support out of order
78 // memory transactions. The Memory Fence is mainly used to make sure IO
/freebsd/contrib/tcsh/
H A Dcsh-mode.el365 (let ((fence-post)
374 (let ((fence-post (save-excursion (end-of-line) (point))))
375 (cond ((re-search-forward csh-switch-re fence-post t)
380 ((re-search-forward csh-case-item-re fence-post t)
395 (setq fence-post (save-excursion (end-of-line) (point)))
413 (re-search-forward "(" fence-post t)
415 (re-search-forward "[^ \t]+[ \t]+" fence-post t)))
423 ((re-search-forward csh-keywords-re fence-post t)
432 ((re-search-forward csh-case-default-re fence-post t)
447 (re-search-forward csh-case-item-re fence-post t)
/freebsd/crypto/openssl/include/internal/
H A Drefcount.h47 * serialized. And any kind of serialization implies a release fence. This
53 * otherwise imply an acquire fence. Hence conditional acquire fence...
/freebsd/sys/sys/
H A Dsmr.h133 * only the observed wr_seq is stale, the fence still orders in smr_enter()
212 * visible. The fence compiles away on amd64. Another in smr_lazy_exit()
213 * alternative would be to omit the fence but store the exit in smr_lazy_exit()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86LoadValueInjectionRetHardening.cpp95 MachineInstr *Fence = in runOnMachineFunction()
97 addRegOffset(BuildMI(MBB, Fence, DebugLoc(), TII->get(X86::SHL64mi)), in runOnMachineFunction()
96 MachineInstr *Fence = runOnMachineFunction() local
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.td692 def FENCE : RVInstI<0b000, OPC_MISC_MEM, (outs),
694 "fence", "$pred, $succ">, Sched<[]> {
703 def FENCE_TSO : RVInstI<0b000, OPC_MISC_MEM, (outs), (ins), "fence.tso", "">, Sched<[]> {
709 def FENCE_I : RVInstI<0b001, OPC_MISC_MEM, (outs), (ins), "fence.i", "">, Sched<[]> {
952 def : InstAlias<"fence", (FENCE 0xF, 0xF)>; // 0xF == iorw
955 def : InstAlias<"pause", (FENCE 0x1, 0x0)>; // 0x1 == w
1725 // fence acquire -> fence r, rw
1726 def : Pat<(atomic_fence (XLenVT 4), (timm)), (FENCE 0b10, 0b11)>;
1727 // fence release -> fence rw, w
1728 def : Pat<(atomic_fence (XLenVT 5), (timm)), (FENCE 0b11, 0b1)>;
[all …]
/freebsd/sys/contrib/ck/include/
H A Dck_epoch.h191 * We can get away without a fence here due to the monotonic nature
225 /* Store fence is implied by push operation. */ in ck_epoch_call_strict()
/freebsd/contrib/llvm-project/openmp/runtime/src/
H A Dkmp_os.h456 /* General purpose fence types for memory operations */
458 kmp_no_fence, /* No memory fence */
459 kmp_acquire_fence, /* Acquire (read) memory fence */
460 kmp_release_fence, /* Release (write) memory fence */
461 kmp_full_fence /* Full (read+write) memory fence */
1069 // fence-style instructions do not exist, but lock; xaddl $0,(%rsp) can be used.
1071 // * If the compiler generates NGO stores it also generates the fence
1072 // * If users hand-code NGO stores they should insert the fence

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