| /linux/Documentation/devicetree/bindings/clock/ |
| H A D | amlogic,c3-peripherals-clkc.yaml | 29 - description: input fclk div 2
30 - description: input fclk div 2p5
31 - description: input fclk div 3
32 - description: input fclk div 4
33 - description: input fclk div 5
34 - description: input fclk div 7
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| H A D | zynq-7000.txt | 26 - fclk-enable : Bit mask to enable FCLKs statically at boot time.
28 FCLK will only be enabled if it is actually running at
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| /linux/drivers/usb/host/ |
| H A D | ehci-sh.c | 13 struct clk *iclk, *fclk; member
114 priv->fclk = devm_clk_get(&pdev->dev, "usb_fck"); in ehci_hcd_sh_probe()
115 if (IS_ERR(priv->fclk)) in ehci_hcd_sh_probe()
116 priv->fclk = NULL; in ehci_hcd_sh_probe()
122 ret = clk_enable(priv->fclk); in ehci_hcd_sh_probe()
144 clk_disable(priv->fclk); in ehci_hcd_sh_probe()
162 clk_disable(priv->fclk); in ehci_hcd_sh_remove()
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| H A D | ohci-at91.c | 54 struct clk *fclk; member
78 clk_set_rate(ohci_at91->fclk, 48000000); in at91_start_clock()
81 clk_prepare_enable(ohci_at91->fclk); in at91_start_clock()
90 clk_disable_unprepare(ohci_at91->fclk); in at91_stop_clock()
215 ohci_at91->fclk = devm_clk_get(dev, "uhpck"); in usb_hcd_at91_probe()
216 if (IS_ERR(ohci_at91->fclk)) { in usb_hcd_at91_probe()
218 retval = PTR_ERR(ohci_at91->fclk); in usb_hcd_at91_probe()
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| /linux/Documentation/devicetree/bindings/display/ti/ |
| H A D | ti,omap4-dss.txt | 14 - clocks: handle to fclk
36 - clocks: handle to fclk
51 - clocks: handles to fclk and iclk
67 - clocks: handle to fclk
88 - clocks: handles to fclk and pll clock
111 - clocks: handles to fclk and pll clock
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| H A D | ti,omap3-dss.txt | 14 - clocks: handle to fclk
37 - clocks: handle to fclk
52 - clocks: handles to fclk and iclk
64 - clocks: handle to fclk
82 - clocks: handles to fclk and pll clock
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| H A D | ti,omap5-dss.txt | 14 - clocks: handle to fclk
36 - clocks: handle to fclk
51 - clocks: handles to fclk and iclk
69 - clocks: handles to fclk and pll clock
92 - clocks: handles to fclk and pll clock
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| H A D | ti,dra7-dss.txt | 14 - clocks: handle to fclk
47 - clocks: handle to fclk
66 - clocks: handles to fclk and pll clock
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| /linux/drivers/media/dvb-frontends/ |
| H A D | s5h1420.c | 39 u32 fclk; member
368 tmp = state->fclk / tmp; in s5h1420_read_status()
475 do_div(val, (state->fclk / 1000)); in s5h1420_setsymbolrate()
501 * divide fclk by 1000000 to get the correct value. */ in s5h1420_setfreqoffset()
502 val = -(int) ((freqoffset * (1<<24)) / (state->fclk / 1000000)); in s5h1420_setfreqoffset()
529 * divide fclk by 1000000 to get the correct value. */ in s5h1420_getfreqoffset()
530 val = (((-val) * (state->fclk/1000000)) / (1<<24)); in s5h1420_getfreqoffset()
666 /* set s5h1420 fclk PLL according to desired symbol rate */ in s5h1420_set_frontend()
668 state->fclk = 80000000; in s5h1420_set_frontend()
670 state->fclk = 59000000; in s5h1420_set_frontend()
[all …]
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| H A D | cx24110.c | 50 {0x07,0x01}, /* @ Fclk, i.e. sampling clock, 60MHz */
231 u32 tmp, fclk, BDRI; in cx24110_set_symbolrate() local
245 and set the PLL accordingly (R07[1:0] Fclk, R06[7:4] PLLmult, in cx24110_set_symbolrate()
251 fclk=90999000UL/2; in cx24110_set_symbolrate()
255 fclk=60666000UL; in cx24110_set_symbolrate()
259 fclk=80888000UL; in cx24110_set_symbolrate()
263 fclk=90999000UL; in cx24110_set_symbolrate()
265 dprintk("cx24110 debug: fclk %d Hz\n",fclk); in cx24110_set_symbolrate()
275 BDRI=fclk>>2; in cx24110_set_symbolrate()
288 dprintk("fclk = %d\n", fclk); in cx24110_set_symbolrate()
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| H A D | mb86a20s.h | 16 * @fclk: Clock frequency. If zero, assumes the default
22 u32 fclk; member
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| /linux/drivers/clk/nuvoton/ |
| H A D | clk-ma35d1-pll.c | 146 unsigned long tmp, fout, fclk, diff; in ma35d1_pll_find_closest() local
153 fclk = div_u64(parent_rate * n, m); in ma35d1_pll_find_closest()
156 fclk = div_u64(fclk, 100); in ma35d1_pll_find_closest()
158 if (fclk < PLL_FCLK_MIN_FREQ || in ma35d1_pll_find_closest()
159 fclk > PLL_FCLK_MAX_FREQ) in ma35d1_pll_find_closest()
162 fout = div_u64(fclk, p); in ma35d1_pll_find_closest()
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| /linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/ |
| H A D | smu_v13_0_1_ppsmc.h | 64 #define PPSMC_MSG_SetSoftMinFclk 0x14 ///< Set hard min for FCLK
68 #define PPSMC_MSG_GetFclkFrequency 0x18 ///< Get FCLK frequency
74 #define PPSMC_MSG_SetSoftMaxFclkByFreq 0x1E ///< Set soft max for FCLK
79 #define PPSMC_MSG_SetHardMinFclkByFreq 0x23 ///< Set hard min for FCLK
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| H A D | smu_v13_0_4_ppsmc.h | 73 #define PPSMC_MSG_SetSoftMinFclk 0x14 ///< Set hard min for FCLK
79 #define PPSMC_MSG_GetFclkFrequency 0x18 ///< Get FCLK frequency
86 #define PPSMC_MSG_SetSoftMaxFclkByFreq 0x1E ///< Set soft max for FCLK
92 #define PPSMC_MSG_SetHardMinFclkByFreq 0x23 ///< Set hard min for FCLK
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| /linux/arch/sh/drivers/pci/ |
| H A D | pcie-sh7786.c | 26 struct clk *fclk, phy_clk; member
224 port->fclk = clk_get(NULL, fclk_name); in pcie_clk_init()
225 if (IS_ERR(port->fclk)) { in pcie_clk_init()
226 ret = PTR_ERR(port->fclk); in pcie_clk_init()
230 clk_enable(port->fclk); in pcie_clk_init()
250 clk_disable(port->fclk); in pcie_clk_init()
251 clk_put(port->fclk); in pcie_clk_init()
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| /linux/drivers/pwm/ |
| H A D | pwm-omap-dmtimer.c | 154 struct clk *fclk; in pwm_omap_dmtimer_config() local
163 fclk = omap->pdata->get_fclk(omap->dm_timer); in pwm_omap_dmtimer_config()
164 if (!fclk) { in pwm_omap_dmtimer_config()
165 dev_err(pwmchip_parent(chip), "invalid pmtimer fclk\n"); in pwm_omap_dmtimer_config()
169 clk_rate = clk_get_rate(fclk); in pwm_omap_dmtimer_config()
171 dev_err(pwmchip_parent(chip), "invalid pmtimer fclk rate\n"); in pwm_omap_dmtimer_config()
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| /linux/drivers/clocksource/ |
| H A D | timer-ti-dm.c | 123 struct clk *fclk; member
418 if (unlikely(!timer) || IS_ERR(timer->fclk)) in omap_dm_timer_set_source()
447 if (clk_hw_get_num_parents(__clk_get_hw(timer->fclk)) < 2) in omap_dm_timer_set_source()
457 ret = clk_set_parent(timer->fclk, parent); in omap_dm_timer_set_source()
729 if (timer && !IS_ERR(timer->fclk)) in omap_dm_timer_get_fclk()
730 return timer->fclk; in omap_dm_timer_get_fclk()
1251 timer->fclk = devm_clk_get(dev, "fck"); in omap_dm_timer_probe()
1252 if (IS_ERR(timer->fclk)) in omap_dm_timer_probe()
1253 return PTR_ERR(timer->fclk); in omap_dm_timer_probe()
1256 ret = devm_clk_notifier_register(dev, timer->fclk, in omap_dm_timer_probe()
[all …]
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| /linux/Documentation/devicetree/bindings/mmc/ |
| H A D | ti-omap-hsmmc.txt | 92 swakeup | | fclk
98 In suspend the fclk is off and the module is dysfunctional. Even register reads
99 will fail. A small logic in the host will request fclk restore, when an
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| /linux/sound/soc/ti/ |
| H A D | omap-dmic.c | 36 struct clk *fclk; member
320 dev_err(dmic->dev, "fclk clk_id (%d) not supported\n", clk_id); in omap_dmic_select_fclk()
330 mux = clk_get_parent(dmic->fclk); in omap_dmic_select_fclk()
476 dmic->fclk = devm_clk_get(dmic->dev, "fck"); in asoc_dmic_probe()
477 if (IS_ERR(dmic->fclk)) { in asoc_dmic_probe()
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| /linux/drivers/i2c/busses/ |
| H A D | i2c-omap.c | 299 * bus is busy. It will be changed to 1 on the next IP FCLK clock. in __omap_i2c_init()
357 struct clk *fclk; in omap_i2c_init() local
376 fclk = clk_get(omap->dev, "fck"); in omap_i2c_init()
377 if (IS_ERR(fclk)) { in omap_i2c_init()
378 error = PTR_ERR(fclk); in omap_i2c_init()
384 fclk_rate = clk_get_rate(fclk); in omap_i2c_init()
385 clk_put(fclk); in omap_i2c_init()
406 * The filter is iclk (fclk for HS) period. in omap_i2c_init()
415 fclk = clk_get(omap->dev, "fck"); in omap_i2c_init()
416 if (IS_ERR(fclk)) { in omap_i2c_init()
[all …]
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| /linux/drivers/clk/zynq/ |
| H A D | clkc.c | 103 static void __init zynq_clk_register_fclk(enum zynq_clk fclk, in zynq_clk_register_fclk() argument
147 clks[fclk] = clk_register_gate(NULL, clk_name, in zynq_clk_register_fclk()
152 if (clk_prepare_enable(clks[fclk])) in zynq_clk_register_fclk()
153 pr_warn("%s: FCLK%u enable failed\n", __func__, in zynq_clk_register_fclk()
154 fclk - fclk0); in zynq_clk_register_fclk()
171 clks[fclk] = ERR_PTR(-ENOMEM); in zynq_clk_register_fclk()
247 of_property_read_u32(np, "fclk-enable", &fclk_enable); in zynq_clk_setup()
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| /linux/drivers/mmc/host/ |
| H A D | omap.c | 131 struct clk * fclk; member
194 clk_enable(host->fclk); in mmc_omap_fclk_enable()
196 clk_disable(host->fclk); in mmc_omap_fclk_enable()
1159 int func_clk_rate = clk_get_rate(host->fclk); in mmc_omap_calc_divisor()
1431 host->fclk = clk_get(&pdev->dev, "fck"); in mmc_omap_probe()
1432 if (IS_ERR(host->fclk)) { in mmc_omap_probe()
1433 ret = PTR_ERR(host->fclk); in mmc_omap_probe()
1437 ret = clk_prepare(host->fclk); in mmc_omap_probe()
1511 clk_unprepare(host->fclk); in mmc_omap_probe()
1513 clk_put(host->fclk); in mmc_omap_probe()
[all …]
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| /linux/drivers/clk/imx/ |
| H A D | clk-imx1.c | 23 "prem", "fclk", };
51 clk[IMX1_CLK_FCLK] = imx_clk_divider("fclk", "mpll_gate", CCM_CSCR, 15, 1); in mx1_clocks_init_dt()
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| /linux/drivers/iio/adc/ |
| H A D | ad7192.c | 209 u32 fclk; member
517 st->fclk = AD7192_INT_FREQ_MHZ; in ad7192_clock_setup()
529 st->fclk = clk_get_rate(st->mclk); in ad7192_clock_setup()
530 if (!ad7192_valid_external_frequency(st->fclk)) in ad7192_clock_setup()
543 st->fclk = AD7192_INT_FREQ_MHZ; in ad7192_clock_setup()
559 st->fclk = clk_get_rate(st->mclk); in ad7192_clock_setup()
560 if (!ad7192_valid_external_frequency(st->fclk)) in ad7192_clock_setup()
763 return DIV_ROUND_CLOSEST(st->fclk, in ad7192_compute_f_adc()
771 return DIV_ROUND_CLOSEST(st->fclk, in ad7192_get_f_adc()
985 div = st->fclk / (val * ad7192_get_f_order(st) * 1024); in __ad7192_write_raw()
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| /linux/arch/arm64/boot/dts/ti/ |
| H A D | k3-am64-mcu.dtsi | 60 clock-names = "fclk";
70 clock-names = "fclk";
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