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/linux/Documentation/scheduler/
H A Dschedutil.rst15 individual tasks to task-group slices to CPU runqueues. As the basis for this
31 Note that blocked tasks still contribute to the aggregates (task-group slices
51 Dynamic Voltage and Frequency Scaling (DVFS) ratio and one microarch ratio.
53 For simple DVFS architectures (where software is in full control) we trivially
57 r_dvfs := -----
60 For more dynamic systems where the hardware is in control of DVFS we use
61 hardware counters (Intel APERF/MPERF, ARMv8.4-AMU) to provide us this ratio.
65 f_cur := ----- * P0
68 4C-turbo; if available and turbo enabled
69 f_max := { 1C-turbo; if turbo enabled
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H A Dsched-util-clamp.rst1 .. SPDX-License-Identifier: GPL-2.0
57 foreground, top-app, etc. Util clamp can be used to constrain how much
60 the ones belonging to the currently active app (top-app group). Beside this
65 1. The big cores are free to run top-app tasks immediately. top-app
106 Note that by design RT tasks don't have per-task PELT signal and must always
107 run at a constant frequency to combat undeterministic DVFS rampup delays.
114 See :ref:`section 3.4 <uclamp-default-values>` for default values and
115 :ref:`3.4.1 <sched-util-clamp-min-rt-default>` on how to change RT tasks
150 task on the rq to only a subset of tasks on the top-most bucket.
157 uclamp value of the rq. See :ref:`section 2.1 <uclamp-buckets>` for details on
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/linux/Documentation/devicetree/bindings/opp/
H A Dopp-v2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Viresh Kumar <viresh.kumar@linaro.org>
13 - $ref: opp-v2-base.yaml#
17 const: operating-points-v2
22 - |
24 * Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states
28 #address-cells = <1>;
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/linux/drivers/mailbox/
H A Dmtk-gpueb-mailbox.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * - Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
44 * struct mtk_gpueb_mbox_chan - per-channel runtime data
60 * struct mtk_gpueb_mbox_chan_desc - per-channel constant data
83 * mtk_gpueb_mbox_read_rx - read RX buffer from MMIO into channel's RX buffer
89 memcpy_fromio(buf, chan->ebm->mbox_mmio + chan->c->rx_offset, chan->c->rx_len); in mtk_gpueb_mbox_read_rx()
97 rx_sts = readl(ch->ebm->mbox_ctl + GPUEB_MBOX_CTL_RX_STS); in mtk_gpueb_mbox_isr()
99 if (rx_sts & BIT(ch->num)) { in mtk_gpueb_mbox_isr()
100 if (!atomic_cmpxchg(&ch->rx_status, 0, GPUEB_MBOX_FULL | GPUEB_MBOX_BLOCKED)) in mtk_gpueb_mbox_isr()
112 status = atomic_cmpxchg(&ch->rx_status, GPUEB_MBOX_FULL | GPUEB_MBOX_BLOCKED, in mtk_gpueb_mbox_thread()
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/linux/Documentation/cpu-freq/
H A Dcpu-drivers.rst1 .. SPDX-License-Identifier: GPL-2.0
10 - Dominik Brodowski <linux@brodo.de>
11 - Rafael J. Wysocki <rafael.j.wysocki@intel.com>
12 - Viresh Kumar <viresh.kumar@linaro.org>
18 1.2 Per-CPU Initialization
31 So, you just got a brand-new CPU / chipset with datasheets and want to
37 ------------------
46 .name - The name of this driver.
48 .init - A pointer to the per-policy initialization function.
50 .verify - A pointer to a "verification" function.
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/linux/drivers/gpu/drm/imagination/
H A Dpvr_rogue_fwif_sf.h1 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
47 * - --- ---- ---- ---- ---- ---- ---- ----
48 * 0-11: id number
49 * 12-15: group id number
50 * 16-19: number of parameters
51 * 20-27: unused
52 * 28-30: active: identify SF packet, otherwise regular int32
114 "UFO PR-Check: [0x%08.8x] is 0x%08.8x requires >= 0x%08.8x" },
116 "UFO SPM PR-Checks for FWCtx 0x%08.8x" },
118 …"UFO SPM special PR-Check: [0x%08.8x] is 0x%08.8x requires >= ????????, [0x%08.8x] is ???????? req…
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H A Dpvr_rogue_fwif.h1 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
42 /* String used in pvrdebug -h output */
140 /* Firmware per-DM HWR states */
155 /* DM was identified as over-running and causing HWR */
157 /* DM was innocently affected by another DM over-running which caused HWR */
270 /* Identify whether MC config is P-P or P-S */
274 /* per-os firmware shared data */
297 /* Firmware trace time-stamp field breakup */
303 /* Extra debug-info (16 bits) */
307 /* Debug-info sub-fields */
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/linux/drivers/gpu/drm/panthor/
H A Dpanthor_device.h1 /* SPDX-License-Identifier: GPL-2.0 or MIT */
10 #include <linux/io-pgtable.h>
37 * struct panthor_soc_data - Panthor SoC Data
48 * enum panthor_device_pm_state - PM state
65 * struct panthor_irq - IRQ data
84 * enum panthor_device_profiling_mode - Profiling state
103 * struct panthor_device - Panthor device
139 /** @hw: GPU-specific data. */
184 * @fast: True if the post_reset logic can proceed with a fast reset.
186 * A fast reset is just a reset where the driver doesn't reload the FW sections.
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/linux/drivers/cpufreq/
H A Dscmi-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018-2021 ARM Ltd.
11 #include <linux/clk-provider.h>
50 priv = policy->driver_data; in scmi_cpufreq_get_rate()
52 ret = perf_ops->freq_get(ph, priv->domain_id, &rate, false); in scmi_cpufreq_get_rate()
59 * perf_ops->freq_set is not a synchronous, the actual OPP change will
66 struct scmi_data *priv = policy->driver_data; in scmi_cpufreq_set_target()
67 u64 freq = policy->freq_table[index].frequency; in scmi_cpufreq_set_target()
69 return perf_ops->freq_set(ph, priv->domain_id, freq * 1000, false); in scmi_cpufreq_set_target()
75 struct scmi_data *priv = policy->driver_data; in scmi_cpufreq_fast_switch()
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H A Dintel_pstate.c1 // SPDX-License-Identifier: GPL-2.0-only
38 #include <asm/intel-family.h>
56 #define ONE_EIGHTH_FP ((int64_t)1 << (FRAC_BITS - 3))
78 mask = (1 << FRAC_BITS) - 1; in ceiling_fp()
95 * struct sample - Store performance sample
122 * struct pstate_data - Store P state data
129 * @perf_ctl_scaling: PERF_CTL P-state to frequency scaling factor
152 * struct vid_data - Stores voltage information data
157 * @ratio: Ratio of (vid max - vid min) /
158 * (max P state - Min P State)
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/linux/arch/arm/boot/dts/nvidia/
H A Dtegra30.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra30-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra30-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
8 #include <dt-bindings/thermal/thermal.h>
10 #include "tegra30-peripherals-opp.dtsi"
14 interrupt-parent = <&lic>;
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/linux/include/linux/
H A Dcpufreq.h1 /* SPDX-License-Identifier: GPL-2.0-only */
6 * (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de>
49 /* in 10^(-9) s = nanoseconds */
94 * - Any routine that wants to read from the policy structure will
96 * - Any routine that will write to the policy structure and/or may take away
103 * Fast switch flags:
104 * - fast_switch_possible should be set by the driver if it can
107 * - fast_switch_enabled is to be set by governors that support fast
134 * Remote DVFS flag (Not added to the driver structure as we don't want
137 * Should be set if CPUs can do DVFS on behalf of other CPUs from
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/linux/kernel/sched/
H A Dcpufreq_schedutil.c1 // SPDX-License-Identifier: GPL-2.0
3 * CPUFreq governor based on scheduler-provided CPU utilization data.
30 /* The next fields are only needed if fast switch cannot be used: */
54 /* The field below is for single-CPU policies only: */
69 * Since cpufreq_update_util() is called with rq->lock held for in sugov_should_update_freq()
70 * the @target_cpu, our per-CPU data is fully serialized. in sugov_should_update_freq()
72 * However, drivers cannot in general deal with cross-CPU in sugov_should_update_freq()
74 * sugov_update_commit() call may not for the fast switching platforms. in sugov_should_update_freq()
83 if (!cpufreq_this_cpu_can_update(sg_policy->policy)) in sugov_should_update_freq()
86 if (unlikely(READ_ONCE(sg_policy->limits_changed))) { in sugov_should_update_freq()
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H A Dfair.c1 // SPDX-License-Identifier: GPL-2.0
44 #include <linux/memory-tiers.h>
62 * The initial- and re-scaling of tunables is configurable
66 * SCHED_TUNABLESCALING_NONE - unscaled, always *1
67 * SCHED_TUNABLESCALING_LOG - scaled logarithmically, *1+ilog(ncpus)
68 * SCHED_TUNABLESCALING_LINEAR - scaled linear, *ncpus
75 * Minimal preemption granularity for CPU-bound tasks:
96 return -cpu; in arch_asym_cpu_priority()
116 * Amount of runtime to allocate from global (tg) to local (per-cfs_rq) pool
167 lw->weight += inc; in update_load_add()
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/linux/drivers/memory/samsung/
H A Dexynos5422-dmc.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/devfreq-event.h>
101 * struct dmc_opp_table - Operating level desciption
113 * struct exynos5_dmc - main structure describing DMC device
196 __val = (t_val) << (timing)->bit_beg; \
220 TIMING_FIELD("tW2W-C2C", 14, 14),
221 TIMING_FIELD("tR2R-C2C", 12, 12),
243 for (i = 0; i < dmc->num_counters; i++) { in exynos5_counters_set_event()
244 if (!dmc->counter[i]) in exynos5_counters_set_event()
246 ret = devfreq_event_set_event(dmc->counter[i]); in exynos5_counters_set_event()
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/linux/drivers/clk/tegra/
H A Dclk-dfll.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * clk-dfll.c - Tegra DFLL clock source common code
5 * Copyright (C) 2012-2019 NVIDIA Corporation. All rights reserved.
12 * "CL-DVFS". To try to avoid confusion, this code refers to them
16 * supply voltage noise. Tegra124 uses it to clock the fast CPU
18 * DFLL can be operated in either open-loop mode or closed-loop mode.
19 * In open-loop mode, the DFLL generates an output clock appropriate
20 * to the supply voltage. In closed-loop mode, when configured with a
27 * performance-measurement code and any code that relies on the CPU
32 #include <linux/clk-provider.h>
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