| /freebsd/sys/contrib/device-tree/Bindings/memory-controllers/ |
| H A D | nvidia,tegra186-mc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra186 (and later) SoC Memory Controller
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 The NVIDIA Tegra186 SoC features a 128 bit memory controller that is split
16 handles memory requests for 40-bit virtual addresses from internal clients
17 and arbitrates among them to allocate memory bandwidth.
[all …]
|
| H A D | nvidia,tegra210-emc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra210-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra210 SoC External Memory Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The EMC interfaces with the off-chip SDRAM to service the request stream
15 sent from the memory controller.
19 const: nvidia,tegra210-emc
[all …]
|
| H A D | st,stm32-fmc2-ebi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics Flexible Memory Controller 2 (FMC2)
11 asynchronous static devices (such as PSNOR, PSRAM or other memory-mapped
14 - to translate AXI transactions into the appropriate external device
16 - to meet the access time requirements of the external devices
17 All external devices share the addresses, data and control signals with the
18 controller. Each external device is accessed by means of a unique Chip
[all …]
|
| H A D | nvidia,tegra20-emc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra20-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra20 SoC External Memory Controller
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
15 The External Memory Controller (EMC) interfaces with the off-chip SDRAM to
16 service the request stream sent from Memory Controller. The EMC also has
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/clock/ |
| H A D | nvidia,tegra124-car.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/nvidia,tegra124-car.yaml#
5 $schema: http://devicetree.org/meta-schema
[all...] |
| H A D | rockchip,rk3368-cru.txt | 3 The RK3368 clock controller generates and supplies clock to various
4 controllers within the SoC and also implements a reset controller for SoC
9 - compatible: should be "rockchip,rk3368-cru"
10 - reg: physical base address of the controller and length of memory mapped
12 - #clock-cells: should be 1.
13 - #reset-cells: should be 1.
17 - rockchip,grf: phandle to the syscon managing the "general register files"
22 preprocessor macros in the dt-bindings/clock/rk3368-cru.h headers and can be
26 External clocks:
30 clock-output-names:
[all …]
|
| H A D | nuvoton,npcm750-clk.txt | 1 * Nuvoton NPCM7XX Clock Controller
3 Nuvoton Poleg BMC NPCM7XX contains an integrated clock controller, which
6 External clocks:
10 clk_sysbypck are inputs to the clock controller.
11 clk_rg1refck, clk_rg2refck and clk_xin are external clocks suppling the
17 dt-bindings/clock/nuvoton,npcm7xx-clock.h
20 Required Properties of clock controller:
22 - compatible: "nuvoton,npcm750-clk" : for clock controller of Nuvoton
25 - reg: physical base address of the clock controller and length of
26 memory mapped region.
[all …]
|
| H A D | rockchip,rv1108-cru.txt | 3 The RV1108 clock controller generates and supplies clock to various
4 controllers within the SoC and also implements a reset controller for SoC
9 - compatible: should be "rockchip,rv1108-cru"
10 - reg: physical base address of the controller and length of memory mapped
12 - #clock-cells: should be 1.
13 - #reset-cells: should be 1.
17 - rockchip,grf: phandle to the syscon managing the "general register files"
22 preprocessor macros in the dt-bindings/clock/rv1108-cru.h headers and can be
26 External clocks:
30 clock-output-names:
[all …]
|
| H A D | rockchip,rk3288-cru.txt | 3 The RK3288 clock controller generates and supplies clock to various
4 controllers within the SoC and also implements a reset controller for SoC
8 different so another dt-compatible is available. Noticed that it is only
14 - compatible: should be "rockchip,rk3288-cru" or "rockchip,rk3288w-cru" in
16 - reg: physical base address of the controller and length of memory mapped
18 - #clock-cells: should be 1.
19 - #reset-cells: should be 1.
23 - rockchip,grf: phandle to the syscon managing the "general register files"
28 preprocessor macros in the dt-bindings/clock/rk3288-cru.h headers and can be
32 External clocks:
[all …]
|
| H A D | samsung,s3c2443-clock.txt | 1 * Samsung S3C2443 Clock Controller
3 The S3C2443 clock controller generates and supplies clock to various controllers
9 - compatible: should be one of the following.
10 - "samsung,s3c2416-clock" - controller compatible with S3C2416 SoC.
11 - "samsung,s3c2443-clock" - controller compatible with S3C2443 SoC.
12 - "samsung,s3c2450-clock" - controller compatible with S3C2450 SoC.
13 - reg: physical base address of the controller and length of memory mapped
15 - #clock-cells: should be 1.
22 dt-bindings/clock/s3c2443.h header and can be used in device
25 External clocks:
[all …]
|
| H A D | samsung,exynos850-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,exynos850-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos850 SoC clock controller
10 - Sam Protsenko <semen.protsenko@linaro.org>
11 - Chanwoo Choi <cw00.choi@samsung.com>
12 - Krzysztof Kozlowski <krzk@kernel.org>
13 - Sylwester Nawrocki <s.nawrocki@samsung.com>
14 - Tomasz Figa <tomasz.figa@gmail.com>
[all …]
|
| H A D | rockchip,rk3228-cru.txt | 3 The RK3228 clock controller generates and supplies clock to various
4 controllers within the SoC and also implements a reset controller for SoC
9 - compatible: should be "rockchip,rk3228-cru"
10 - reg: physical base address of the controller and length of memory mapped
12 - #clock-cells: should be 1.
13 - #reset-cells: should be 1.
17 - rockchip,grf: phandle to the syscon managing the "general register files"
22 preprocessor macros in the dt-bindings/clock/rk3228-cru.h headers and can be
26 External clocks:
30 clock-output-names:
[all …]
|
| H A D | samsung,s5pv210-clock.txt | 1 * Samsung S5P6442/S5PC110/S5PV210 Clock Controller
4 controller, which generates and supplies clock to various controllers
9 - compatible: should be one of following:
10 - "samsung,s5pv210-clock" : for clock controller of Samsung
12 - "samsung,s5p6442-clock" : for clock controller of Samsung
15 - reg: physical base address of the controller and length of memory mapped
18 - #clock-cells: should be 1.
21 dt-bindings/clock/s5pv210.h header and can be used in device tree sources.
23 External clocks:
27 clock-output-names:
[all …]
|
| H A D | rockchip,rk3399-cru.txt | 3 The RK3399 clock controller generates and supplies clock to various
4 controllers within the SoC and also implements a reset controller for SoC
9 - compatible: PMU for CRU should be "rockchip,rk3399-pmucru"
10 - compatible: CRU should be "rockchip,rk3399-cru"
11 - reg: physical base address of the controller and length of memory mapped
13 - #clock-cells: should be 1.
14 - #reset-cells: should be 1.
18 - rockchip,grf: phandle to the syscon managing the "general register files".
24 preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be
28 External clocks:
[all …]
|
| H A D | rockchip,rk3188-cru.txt | 3 The RK3188/RK3066 clock controller generates and supplies clock to various
4 controllers within the SoC and also implements a reset controller for SoC
9 - compatible: should be "rockchip,rk3188-cru", "rockchip,rk3188a-cru" or
10 "rockchip,rk3066a-cru"
11 - reg: physical base address of the controller and length of memory mapped
13 - #clock-cells: should be 1.
14 - #reset-cells: should be 1.
18 - rockchip,grf: phandle to the syscon managing the "general register files"
23 preprocessor macros in the dt-bindings/clock/rk3188-cru.h and
24 dt-bindings/clock/rk3066-cru.h headers and can be used in device tree sources.
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/net/can/ |
| H A D | cc770.txt | 1 Memory mapped Bosch CC770 and Intel AN82527 CAN controller
3 Note: The CC770 is a CAN controller from Bosch, which is 100%
8 - compatible : should be "bosch,cc770" for the CC770 and "intc,82527"
11 - reg : should specify the chip select, address offset and size required
12 to map the registers of the controller. The size is usually 0x80.
14 - interrupts : property with a value describing the interrupt source
15 (number and sensitivity) required for the controller.
19 - bosch,external
[all...] |
| /freebsd/sys/contrib/device-tree/Bindings/usb/ |
| H A D | msm-hsusb.txt | 6 - compatible: Should contain "qcom,ehci-host"
7 - regs: offset and length of the register set in the memory map
8 - usb-phy: phandle for the PHY device
10 Example EHCI controller device node:
13 compatible = "qcom,ehci-host";
15 usb-phy = <&usb_otg>;
21 - compatibl
[all...] |
| /freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/ |
| H A D | sifive,plic-1.0.0.txt | 1 SiFive Platform-Level Interrupt Controller (PLIC)
2 -------------------------------------------------
4 SiFive SOCs include an implementation of the Platform-Level Interrupt Controller
5 (PLIC) high-level specification in the RISC-V Privileged Architecture
6 specification. The PLIC connects all external interrupts in the system to all
7 hart contexts in the system, via the external interrupt source in each hart.
10 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
13 Each interrupt can be enabled on per-context basis. Any context can claim
21 While the PLIC supports both edge-triggered and level-triggered interrupts,
23 specified in the PLIC device-tree binding.
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/dma/ |
| H A D | socionext,uniphier-xdmac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/socionext,uniphier-xdmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier external DMA controller
10 This describes the devicetree bindings for an external DMA engine to perform
11 memory-to-memory or peripheral-to-memory data transfer capable of supporting
15 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
18 - $ref: dma-controller.yaml#
22 const: socionext,uniphier-xdmac
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/devfreq/ |
| H A D | nvidia,tegra30-actmon.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/devfreq/nvidia,tegra30-actmon.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
17 which the external memory needs to be clocked in order to serve all requests
23 - nvidia,tegra30-actmon
24 - nvidia,tegra114-actmon
[all …]
|
| /freebsd/share/man/man4/ |
| H A D | ahc.4 | 37 .Bd -ragged -offset indent
48 .Bd -literal -offset indent
60 fast, ultra or ultra2 synchronous transfers depending on controller type,
64 .Tn SCSI-Select
72 For systems that store non-volatile settings in a system specific manner
73 rather than a serial eeprom directly connected to the aic7xxx controller,
78 many chip-down motherboard configurations.
88 .Bd -ragged -offset indent
89 .Bl -column "aic7895CX" "MIPSX" "PCI/64X" "MaxSyncX" "MaxWidthX" "SCBsX" "2 3 4 5 6 7 8X"
106 .Bl -enum -compact
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/bus/ |
| H A D | nvidia,tegra20-gmi.txt | 1 Device tree bindings for NVIDIA Tegra Generic Memory Interface bus
3 The Generic Memory Interface bus enables memory transfers between internal and
4 external memory. Can be used to attach various high speed devices such as
10 - compatible : Should contain one of the following:
11 For Tegra20 must contain "nvidia,tegra20-gmi".
12 For Tegra30 must contain "nvidia,tegra30-gmi".
13 - reg: Should contain GMI controller registers location and length.
14 - clocks: Must contain an entry for each entry in clock-names.
15 - clock-names: Must include the following entries: "gmi"
16 - resets : Must contain an entry for each entry in reset-names.
[all …]
|
| /freebsd/lib/libpmc/pmu-events/arch/x86/ivybridge/ |
| H A D | uncore.json | 19 "BriefDescription": "A snoop invalidates a non-modified line in some processor core.",
20 "PublicDescription": "A snoop invalidates a non-modified line in some processor core.",
31 "BriefDescription": "A snoop hits a non-modified line in some processor core.",
32 "PublicDescription": "A snoop hits a non-modified line in some processor core.",
67 …"BriefDescription": "Filter on cross-core snoops initiated by this Cbox due to external snoop requ…
68 …"PublicDescription": "Filter on cross-core snoops initiated by this Cbox due to external snoop req…
79 …"BriefDescription": "Filter on cross-core snoops initiated by this Cbox due to processor core memo…
80 …"PublicDescription": "Filter on cross-core snoops initiated by this Cbox due to processor core mem…
91 "BriefDescription": "Filter on cross-core snoops initiated by this Cbox due to LLC eviction.",
92 "PublicDescription": "Filter on cross-core snoops initiated by this Cbox due to LLC eviction.",
[all …]
|
| /freebsd/lib/libpmc/pmu-events/arch/x86/sandybridge/ |
| H A D | uncore.json | 19 "BriefDescription": "A snoop invalidates a non-modified line in some processor core.",
20 "PublicDescription": "A snoop invalidates a non-modified line in some processor core.",
31 "BriefDescription": "A snoop hits a non-modified line in some processor core.",
32 "PublicDescription": "A snoop hits a non-modified line in some processor core.",
67 …"BriefDescription": "Filter on cross-core snoops initiated by this Cbox due to external snoop requ…
68 …"PublicDescription": "Filter on cross-core snoops initiated by this Cbox due to external snoop req…
79 …"BriefDescription": "Filter on cross-core snoops initiated by this Cbox due to processor core memo…
80 …"PublicDescription": "Filter on cross-core snoops initiated by this Cbox due to processor core mem…
91 "BriefDescription": "Filter on cross-core snoops initiated by this Cbox due to LLC eviction.",
92 "PublicDescription": "Filter on cross-core snoops initiated by this Cbox due to LLC eviction.",
[all …]
|
| /freebsd/sys/dts/arm/ |
| H A D | annapurna-alpine.dts | 1 /*-
28 /dts-v1/;
32 #address-cells = <1>;
33 #size-cells = <1>;
40 #address-cells = <1>;
41 #size-cells = <0>;
45 compatible = "arm,cortex-a15";
47 d-cache-line-size = <64>; // 64 bytes
48 i-cache-line-size = <64>; // 64 bytes
49 d-cache-size = <0x8000>; // L1, 32K
[all …]
|