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/linux/Documentation/devicetree/bindings/clock/
H A Dingenic,cgu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The CGU in an Ingenic SoC provides all the clocks generated on-chip. It
16 - Paul Cercueil <paul@crapouillou.net>
23 - ingenic,jz4740-cgu
24 - ingenic,jz4725b-cgu
25 - ingenic,jz4755-cgu
26 - ingenic,jz4760-cgu
27 - ingenic,jz4760b-cgu
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dcpsw-phy-sel.txt1 TI CPSW Phy mode Selection Device Tree Bindings (DEPRECATED)
2 -----------------------------------------------
5 - compatible : Should be "ti,am3352-cpsw-phy-sel" for am335x platform and
6 "ti,dra7xx-cpsw-phy-sel" for dra7xx platform
7 "ti,am43xx-cpsw-phy-sel" for am43xx platform
8 - reg : physical base address and size of the cpsw
10 - reg-names : names of the register map given in "reg" node
13 -rmii-clock-ext : If present, the driver will configure the RMII
18 phy_sel: cpsw-phy-sel@44e10650 {
19 compatible = "ti,am3352-cpsw-phy-sel";
[all …]
/linux/drivers/net/phy/
H A Dsfp.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/mdio/mdio-i2c.h>
13 #include <linux/phy.h>
149 "mod-def0",
151 "tx-fault",
152 "tx-disable",
153 "rate-select0",
154 "rate-select1",
166 /* t_start_up (SFF-8431) or t_init (SFF-8472) is the time required for a
167 * non-cooled module to initialise its laser safety circuitry. We wait
[all …]
/linux/arch/mips/boot/dts/ingenic/
H A Djz4780.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ingenic,jz4780-cgu.h>
3 #include <dt-bindings/clock/ingenic,tcu.h>
4 #include <dt-bindings/dma/jz4780-dma.h>
7 #address-cells = <1>;
8 #size-cells = <1>;
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
21 clock-names = "cpu";
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H A Djz4770.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ingenic,jz4770-cgu.h>
3 #include <dt-bindings/clock/ingenic,tcu.h>
6 #address-cells = <1>;
7 #size-cells = <1>;
11 #address-cells = <1>;
12 #size-cells = <0>;
16 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
20 clock-names = "cpu";
24 cpuintc: interrupt-controller {
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H A Dx1830.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ingenic,tcu.h>
3 #include <dt-bindings/clock/ingenic,x1830-cgu.h>
4 #include <dt-bindings/dma/x1830-dma.h>
7 #address-cells = <1>;
8 #size-cells = <1>;
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "ingenic,xburst-fpu2.0-mxu2.0";
21 clock-names = "cpu";
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H A Dx1000.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ingenic,tcu.h>
3 #include <dt-bindings/clock/ingenic,x1000-cgu.h>
4 #include <dt-bindings/dma/x1000-dma.h>
7 #address-cells = <1>;
8 #size-cells = <1>;
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
21 clock-names = "cpu";
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/linux/Documentation/devicetree/bindings/phy/
H A Dphy-miphy28lp.txt1 STMicroelectronics STi MIPHY28LP PHY binding
4 This binding describes a miphy device that is used to control PHY hardware
8 - compatible : Should be "st,miphy28lp-phy".
9 - st,syscfg : Should be a phandle of the system configuration register group
12 Required nodes : A sub-node is required for each channel the controller
14 'reg' and 'reg-names' properties are used inside these
19 - #phy-cells : Should be 1 (See second example)
21 - PHY_TYPE_SATA
22 - PHY_TYPE_PCI
23 - PHY_TYPE_USB3
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H A Dsocionext,uniphier-usb3ss-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3ss-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier USB3 Super-Speed (SS) PHY
10 This describes the devicetree bindings for PHY interfaces built into
12 Although the controller includes High-Speed PHY and Super-Speed PHY,
13 this describes about Super-Speed PHY.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
21 - socionext,uniphier-pro4-usb3-ssphy
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H A Dsocionext,uniphier-usb3hs-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3hs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier USB3 High-Speed (HS) PHY
10 This describes the devicetree bindings for PHY interfaces built into
12 Although the controller includes High-Speed PHY and Super-Speed PHY,
13 this describes about High-Speed PHY.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
21 - socionext,uniphier-pro5-usb3-hsphy
[all …]
H A Dphy-rockchip-naneng-combphy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-rockchip-naneng-combphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SoC Naneng Combo Phy
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,rk3528-naneng-combphy
16 - rockchip,rk3562-naneng-combphy
17 - rockchip,rk3568-naneng-combphy
18 - rockchip,rk3576-naneng-combphy
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/linux/arch/mips/boot/dts/xilfpga/
H A Dnexys4ddr.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
14 stdout-path = "serial0:115200n8";
22 cpuintc: interrupt-controller {
23 #address-cells = <0>;
24 #interrupt-cells = <1>;
25 interrupt-controller;
26 compatible = "mti,cpu-interrupt-controller";
29 axi_intc: interrupt-controller@10200000 {
30 #interrupt-cells = <1>;
[all …]
/linux/arch/arm/boot/dts/nxp/ls/
H A Dls1021a-iot.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2021-2022 NXP
7 /dts-v1/;
11 model = "LS1021A-IOT Board";
12 compatible = "fsl,ls1021a-iot", "fsl,ls1021a";
14 sys_mclk: clock-mclk {
15 compatible = "fixed-clock";
16 #clock-cells = <0>;
17 clock-frequency = <24576000>;
20 reg_3p3v: regulator-3V3 {
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/linux/drivers/net/ethernet/atheros/atl1c/
H A Datl1c_hw.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
37 * 00-0B-6A-F6-00-DC in atl1c_hw_set_mac_addr()
78 /* MAC-address from BIOS is the 1st priority */ in atl1c_get_permanent_address()
79 if (atl1c_read_current_addr(hw, hw->perm_mac_addr)) in atl1c_get_permanent_address()
85 if (hw->nic_type == athr_l1c || hw->nic_type == athr_l2c) { in atl1c_get_permanent_address()
95 if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l2c_b2) { in atl1c_get_permanent_address()
116 return -1; in atl1c_get_permanent_address()
119 if ((hw->nic_type == athr_l1c || hw->nic_type == athr_l2c)) { in atl1c_get_permanent_address()
134 if (atl1c_read_current_addr(hw, hw->perm_mac_addr)) in atl1c_get_permanent_address()
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/linux/drivers/net/wireless/intel/iwlwifi/fw/api/
H A Drx.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2012-2014, 2018-2025 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2015-2017 Intel Deutschland GmbH
10 /* API for pre-9000 hardware */
26 * struct iwl_rx_phy_info - phy info
28 * @non_cfg_phy_cnt: non configurable DSP phy data byte count
29 * @cfg_phy_cnt: configurable DSP phy data byte count
30 * @stat_id: configurable DSP phy data set ID
34 * @beacon_time_stamp: beacon at on-air rise
[all …]
/linux/arch/arm/boot/dts/marvell/
H A Dkirkwood-netxbig.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 * Based on netxbig_v2-setup.c,
14 #include <dt-bindings/leds/leds-netxbig.h>
16 #include "kirkwood-6281.dtsi"
21 stdout-path = &uart0;
33 #address-cells = <1>;
34 #size-cells = <1>;
35 compatible = "mxicy,mx25l4005a", "jedec,spi-nor";
37 spi-max-frequency = <20000000>;
42 label = "u-boot";
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/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6ul-var-som-concerto.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Support for Variscite MX6 Concerto Carrier board with the VAR-SOM-MX6UL
10 #include "imx6ul-var-som.dtsi"
11 #include <dt-bindings/leds/common.h>
14 model = "Variscite VAR-SOM-MX6UL Concerto Board";
15 compatible = "variscite,mx6ulconcerto", "variscite,var-som-imx6ul", "fsl,imx6ul";
18 stdout-path = &uart1;
21 gpio-keys {
22 compatible = "gpio-keys";
23 pinctrl-names = "default";
[all …]
H A Dimx7d-sdb.dts1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 /dts-v1/;
11 compatible = "fsl,imx7d-sdb", "fsl,imx7d";
19 stdout-path = &uart1;
27 gpio-keys {
28 compatible = "gpio-keys";
29 pinctrl-names = "default";
30 pinctrl-0 = <&pinctrl_gpio_keys>;
32 key-volume-up {
36 wakeup-source;
[all …]
/linux/arch/arm64/boot/dts/sprd/
H A Dwhale2.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/clock/sprd,sc9860-clk.h>
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
16 compatible = "simple-bus";
17 #address-cells = <2>;
18 #size-cells = <2>;
66 ap-apb@70000000 {
67 compatible = "simple-bus";
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1028a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2018-2021 NXP
11 /dts-v1/;
12 #include "fsl-ls1028a.dtsi"
16 compatible = "fsl,ls1028a-rdb", "fsl,ls1028a";
38 stdout-path = "serial0:115200n8";
46 sys_mclk: clock-mclk {
47 compatible = "fixed-clock";
48 #clock-cells = <0>;
49 clock-frequency = <25000000>;
[all …]
H A Dimx8qm-mek.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
7 /dts-v1/;
9 #include <dt-bindings/usb/pd.h>
14 compatible = "fsl,imx8qm-mek", "fsl,imx8qm";
17 stdout-path = &lpuart0;
21 /delete-node/ cpu-map;
22 /delete-node/ cpu@100;
23 /delete-node/ cpu@101;
26 thermal-zones {
[all …]
H A Dimx8mm-nitrogen-r2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
11 compatible = "boundary,imx8mm-nitrogen8mm", "fsl,imx8mm";
13 reg_vref_1v8: regulator-vref-1v8 {
14 compatible = "regulator-fixed";
15 regulator-name = "vref-1v8";
16 regulator-min-microvolt = <1800000>;
17 regulator-max-microvolt = <1800000>;
20 reg_vref_3v3: regulator-vref-3v3 {
21 compatible = "regulator-fixed";
[all …]
/linux/drivers/nfc/pn533/
H A Duart.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for NXP PN532 NFC Chip - UART transport layer
38 * no-op to the chip.
52 struct pn532_uart_phy *pn532 = dev->phy; in pn532_uart_send_frame()
56 out->data, out->len, false); in pn532_uart_send_frame()
58 pn532->cur_out_buf = out; in pn532_uart_send_frame()
59 if (pn532->send_wakeup) { in pn532_uart_send_frame()
60 err = serdev_device_write(pn532->serdev, in pn532_uart_send_frame()
67 if (pn532->send_wakeup == PN532_SEND_LAST_WAKEUP) in pn532_uart_send_frame()
68 pn532->send_wakeup = PN532_SEND_NO_WAKEUP; in pn532_uart_send_frame()
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/linux/arch/arm/boot/dts/nxp/vf/
H A Dvf610-twr.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 /dts-v1/;
10 compatible = "fsl,vf610-twr", "fsl,vf610";
22 compatible = "fixed-clock";
23 #clock-cells = <0>;
24 clock-frequency = <24576000>;
28 compatible = "fixed-clock";
29 #clock-cells = <0>;
30 clock-frequency = <50000000>;
34 reg_3p3v: regulator-3p3v {
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/linux/drivers/net/ethernet/altera/
H A Daltera_tse_ethtool.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Ethtool support for Altera Triple-Speed Ethernet MAC driver
3 * Copyright (C) 2008-2014 Altera Corporation. All rights reserved
22 #include <linux/phy.h>
67 u32 rev = ioread32(&priv->mac_dev->megacore_revision); in tse_get_drvinfo()
69 strcpy(info->driver, "altera_tse"); in tse_get_drvinfo()
70 snprintf(info->fw_version, ETHTOOL_FWVERS_LEN, "v%d.%d", in tse_get_drvinfo()
72 sprintf(info->bus_info, "platform"); in tse_get_drvinfo()
87 u64 ext; in tse_fill_stats() local
89 buf[0] = csrrd32(priv->mac_dev, in tse_fill_stats()
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