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/linux/Documentation/devicetree/bindings/clock/
H A Dmediatek,ethsys.yaml4 $id: http://devicetree.org/schemas/clock/mediatek,ethsys.yaml#
7 title: Mediatek ethsys controller
20 - mediatek,mt2701-ethsys
21 - mediatek,mt7622-ethsys
22 - mediatek,mt7629-ethsys
23 - mediatek,mt7981-ethsys
24 - mediatek,mt7986-ethsys
25 - mediatek,mt7988-ethsys
28 - const: mediatek,mt7623-ethsys
29 - const: mediatek,mt2701-ethsys
[all …]
/linux/arch/arm/boot/dts/mediatek/
H A Dmt7629.dtsi430 ethsys: syscon@1b000000 { label
431 compatible = "mediatek,mt7629-ethsys", "syscon";
445 <&ethsys CLK_ETH_ESW_EN>,
446 <&ethsys CLK_ETH_GP0_EN>,
447 <&ethsys CLK_ETH_GP1_EN>,
448 <&ethsys CLK_ETH_GP2_EN>,
449 <&ethsys CLK_ETH_FE_EN>,
471 mediatek,ethsys = <&ethsys>;
H A Dmt2701.dtsi720 ethsys: syscon@1b000000 { label
721 compatible = "mediatek,mt2701-ethsys", "syscon";
734 <&ethsys CLK_ETHSYS_ESW>,
735 <&ethsys CLK_ETHSYS_GP1>,
736 <&ethsys CLK_ETHSYS_GP2>,
739 resets = <&ethsys MT2701_ETHSYS_FE_RST>,
740 <&ethsys MT2701_ETHSYS_GMAC_RST>,
741 <&ethsys MT2701_ETHSYS_PPE_RST>;
744 mediatek,ethsys = <&ethsys>;
H A Dmt7623.dtsi939 ethsys: syscon@1b000000 { label
940 compatible = "mediatek,mt7623-ethsys",
941 "mediatek,mt2701-ethsys",
952 clocks = <&ethsys CLK_ETHSYS_HSDMA>;
967 <&ethsys CLK_ETHSYS_ESW>,
968 <&ethsys CLK_ETHSYS_GP1>,
969 <&ethsys CLK_ETHSYS_GP2>,
972 resets = <&ethsys MT2701_ETHSYS_FE_RST>,
973 <&ethsys MT2701_ETHSYS_GMAC_RST>,
974 <&ethsys MT2701_ETHSYS_PPE_RST>;
[all …]
H A Dmt7623a.dtsi54 resets = <&ethsys MT2701_ETHSYS_MCM_RST>;
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt7988a.dtsi742 ethsys: clock-controller@15000000 { label
743 compatible = "mediatek,mt7988-ethsys", "syscon";
917 clocks = <&ethsys CLK_ETHDMA_CRYPT0_EN>,
918 <&ethsys CLK_ETHDMA_FE_EN>,
919 <&ethsys CLK_ETHDMA_GP2_EN>,
920 <&ethsys CLK_ETHDMA_GP1_EN>,
921 <&ethsys CLK_ETHDMA_GP3_EN>,
925 <&ethsys CLK_ETHDMA_ESW_EN>,
938 <&ethsys CLK_ETHDMA_XGP1_EN>,
939 <&ethsys CLK_ETHDMA_XGP2_EN>,
[all …]
H A Dmt7986a.dtsi494 ethsys: syscon@15000000 { label
495 compatible = "mediatek,mt7986-ethsys",
541 clocks = <&ethsys CLK_ETH_FE_EN>,
542 <&ethsys CLK_ETH_GP2_EN>,
543 <&ethsys CLK_ETH_GP1_EN>,
544 <&ethsys CLK_ETH_WOCPU1_EN>,
545 <&ethsys CLK_ETH_WOCPU0_EN>,
569 mediatek,ethsys = <&ethsys>;
H A Dmt7622.dtsi929 ethsys: clock-controller@1b000000 { label
930 compatible = "mediatek,mt7622-ethsys",
941 clocks = <&ethsys CLK_ETH_HSDMA_EN>;
975 <&ethsys CLK_ETH_ESW_EN>,
976 <&ethsys CLK_ETH_GP0_EN>,
977 <&ethsys CLK_ETH_GP1_EN>,
978 <&ethsys CLK_ETH_GP2_EN>,
990 mediatek,ethsys = <&ethsys>;
/linux/drivers/clk/mediatek/
H A DKconfig54 bool "Clock driver for MediaTek MT2701 ethsys"
57 This driver supports MediaTek MT2701 ethsys clocks.
386 tristate "Clock driver for MediaTek MT7622 ETHSYS"
416 bool "Clock driver for MediaTek MT7629 ETHSYS"
439 tristate "Clock driver for MediaTek MT7981 ETHSYS"
456 tristate "Clock driver for MediaTek MT7986 ETHSYS"
H A Dclk-mt2701-eth.c49 { .compatible = "mediatek,mt2701-ethsys", .data = &eth_desc },
H A Dclk-mt7622-eth.c74 { .compatible = "mediatek,mt7622-ethsys", .data = &eth_desc },
H A Dclk-mt7986-eth.c82 { .compatible = "mediatek,mt7986-ethsys", .data = &eth_desc },
H A Dclk-mt7981-eth.c101 { .compatible = "mediatek,mt7981-ethsys", .data = &eth_desc },
H A Dclk-mt7629-eth.c122 .compatible = "mediatek,mt7629-ethsys",
H A Dclk-mt7988-eth.c131 { .compatible = "mediatek,mt7988-ethsys", .data = &ethdma_desc },
/linux/include/dt-bindings/reset/
H A Dmt7986-resets.h46 /* ETHSYS Subsystem resets */
H A Dmt2701-resets.h75 /* ETHSYS resets */
H A Dmt7622-reset.h76 /* ETHSYS Subsystem resets */
/linux/Documentation/devicetree/bindings/dma/
H A Dmediatek,mt7622-hsdma.yaml59 clocks = <&ethsys CLK_ETHSYS_HSDMA>;
/linux/drivers/net/ethernet/mediatek/
H A Dmtk_eth_soc.c482 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, in mt7621_gmac0_rgmii_adjust()
645 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); in mtk_mac_config()
648 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); in mtk_mac_config()
659 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); in mtk_mac_config()
661 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, in mtk_mac_config()
705 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, in mtk_mac_finish()
3773 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, in ethsys_reset()
3778 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, in ethsys_reset()
3902 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0); in mtk_hw_reset()
3926 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, in mtk_hw_reset()
[all …]
/linux/include/dt-bindings/clock/
H A Dmt7986-clk.h161 /* ETHSYS */
H A Dmt7629-clk.h188 /* ETHSYS */
H A Dmediatek,mt7981-clk.h209 /* ETHSYS */
H A Dmt7622-clk.h264 /* ETHSYS */
/linux/Documentation/devicetree/bindings/net/dsa/
H A Dmediatek,mt7530.yaml169 ethsys.
405 resets = <&ethsys MT2701_ETHSYS_MCM_RST>;

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