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/linux/Documentation/devicetree/bindings/clock/
H A Dmediatek,ethsys.yaml4 $id: http://devicetree.org/schemas/clock/mediatek,ethsys.yaml#
7 title: Mediatek ethsys controller
20 - mediatek,mt2701-ethsys
21 - mediatek,mt7622-ethsys
22 - mediatek,mt7629-ethsys
23 - mediatek,mt7981-ethsys
24 - mediatek,mt7986-ethsys
25 - mediatek,mt7988-ethsys
28 - const: mediatek,mt7623-ethsys
29 - const: mediatek,mt2701-ethsys
[all …]
/linux/arch/arm/boot/dts/mediatek/
H A Dmt7629.dtsi430 ethsys: syscon@1b000000 { label
431 compatible = "mediatek,mt7629-ethsys", "syscon";
445 <&ethsys CLK_ETH_ESW_EN>,
446 <&ethsys CLK_ETH_GP0_EN>,
447 <&ethsys CLK_ETH_GP1_EN>,
448 <&ethsys CLK_ETH_GP2_EN>,
449 <&ethsys CLK_ETH_FE_EN>,
471 mediatek,ethsys = <&ethsys>;
H A Dmt2701.dtsi720 ethsys: syscon@1b000000 { label
721 compatible = "mediatek,mt2701-ethsys", "syscon";
734 <&ethsys CLK_ETHSYS_ESW>,
735 <&ethsys CLK_ETHSYS_GP1>,
736 <&ethsys CLK_ETHSYS_GP2>,
739 resets = <&ethsys MT2701_ETHSYS_FE_RST>,
740 <&ethsys MT2701_ETHSYS_GMAC_RST>,
741 <&ethsys MT2701_ETHSYS_PPE_RST>;
744 mediatek,ethsys = <&ethsys>;
H A Dmt7623.dtsi939 ethsys: syscon@1b000000 { label
940 compatible = "mediatek,mt7623-ethsys",
941 "mediatek,mt2701-ethsys",
952 clocks = <&ethsys CLK_ETHSYS_HSDMA>;
967 <&ethsys CLK_ETHSYS_ESW>,
968 <&ethsys CLK_ETHSYS_GP1>,
969 <&ethsys CLK_ETHSYS_GP2>,
972 resets = <&ethsys MT2701_ETHSYS_FE_RST>,
973 <&ethsys MT2701_ETHSYS_GMAC_RST>,
974 <&ethsys MT2701_ETHSYS_PPE_RST>;
[all …]
H A Dmt7623a.dtsi54 resets = <&ethsys MT2701_ETHSYS_MCM_RST>;
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt7622.dtsi929 ethsys: clock-controller@1b000000 { label
930 compatible = "mediatek,mt7622-ethsys",
941 clocks = <&ethsys CLK_ETH_HSDMA_EN>;
975 <&ethsys CLK_ETH_ESW_EN>,
976 <&ethsys CLK_ETH_GP0_EN>,
977 <&ethsys CLK_ETH_GP1_EN>,
978 <&ethsys CLK_ETH_GP2_EN>,
990 mediatek,ethsys = <&ethsys>;
/linux/include/dt-bindings/reset/
H A Dmt7986-resets.h46 /* ETHSYS Subsystem resets */
H A Dmt2701-resets.h75 /* ETHSYS resets */
H A Dmt7622-reset.h76 /* ETHSYS Subsystem resets */
/linux/Documentation/devicetree/bindings/dma/
H A Dmediatek,mt7622-hsdma.yaml59 clocks = <&ethsys CLK_ETHSYS_HSDMA>;
/linux/drivers/clk/mediatek/
H A Dclk-mt2701-eth.c49 { .compatible = "mediatek,mt2701-ethsys", .data = &eth_desc },
H A Dclk-mt7622-eth.c74 { .compatible = "mediatek,mt7622-ethsys", .data = &eth_desc },
H A Dclk-mt7986-eth.c82 { .compatible = "mediatek,mt7986-ethsys", .data = &eth_desc },
H A Dclk-mt7629-eth.c122 .compatible = "mediatek,mt7629-ethsys",
H A Dclk-mt7988-eth.c131 { .compatible = "mediatek,mt7988-ethsys", .data = &ethdma_desc },
/linux/drivers/net/ethernet/mediatek/
H A Dmtk_eth_soc.c482 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, in mt7621_gmac0_rgmii_adjust()
645 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); in mtk_mac_config()
648 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); in mtk_mac_config()
659 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); in mtk_mac_config()
661 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, in mtk_mac_config()
705 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, in mtk_mac_finish()
3781 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, in ethsys_reset()
3786 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, in ethsys_reset()
3910 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0); in mtk_hw_reset()
3934 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, in mtk_hw_reset()
[all …]
H A Dmtk_eth_soc.h1261 * @ethsys: The register map pointing at the range used to setup
1306 struct regmap *ethsys; member
H A Dmtk_star_emac.c148 /* EthSys Configuration Register */
/linux/include/dt-bindings/clock/
H A Dmt7986-clk.h161 /* ETHSYS */
H A Dmt7629-clk.h188 /* ETHSYS */
H A Dmediatek,mt7981-clk.h209 /* ETHSYS */
H A Dmt7622-clk.h264 /* ETHSYS */
H A Dmt2701-clk.h415 /* ETHSYS */
/linux/Documentation/devicetree/bindings/net/dsa/
H A Dmediatek,mt7530.yaml169 ethsys.
405 resets = <&ethsys MT2701_ETHSYS_MCM_RST>;
/linux/drivers/pmdomain/mediatek/
H A Dmtk-scpsys.c831 .name = "ethsys",