1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/actions,s700-pinctrl.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Actions Semi S700 Pin Controller 8 9maintainers: 10 - Manivannan Sadhasivam <mani@kernel.org> 11 12properties: 13 compatible: 14 const: actions,s700-pinctrl 15 16 reg: 17 maxItems: 1 18 19 clocks: 20 maxItems: 1 21 22 gpio-controller: true 23 24 gpio-line-names: 25 maxItems: 136 26 27 gpio-ranges: true 28 29 '#gpio-cells': 30 const: 2 31 32 interrupt-controller: true 33 34 '#interrupt-cells': 35 const: 2 36 37 interrupts: 38 maxItems: 5 39 description: 40 The interrupt outputs from the controller. There is one GPIO interrupt per 41 GPIO bank. The interrupts must be ordered by bank, starting with 42 bank 0. 43 44additionalProperties: 45 type: object 46 description: Pin configuration subnode 47 additionalProperties: false 48 49 properties: 50 pinmux: 51 description: Configure pin multiplexing. 52 type: object 53 $ref: /schemas/pinctrl/pinmux-node.yaml# 54 additionalProperties: false 55 56 properties: 57 groups: 58 items: 59 enum: [ 60 rgmii_txd23_mfp, rgmii_rxd2_mfp, rgmii_rxd3_mfp, lcd0_d18_mfp, 61 rgmii_txd01_mfp, rgmii_txd0_mfp, rgmii_txd1_mfp, rgmii_txen_mfp, 62 rgmii_rxen_mfp, rgmii_rxd1_mfp, rgmii_rxd0_mfp, rgmii_ref_clk_mfp, 63 i2c1_dummy, i2c2_dummy, i2s_d0_mfp, i2s_pcm1_mfp, i2s0_pcm0_mfp, i2s1_pcm0_mfp, 64 i2s_d1_mfp, ks_in2_mfp, ks_in1_mfp, ks_in0_mfp, ks_in3_mfp, 65 ks_out0_mfp, ks_out1_mfp, ks_out2_mfp, lvds_o_pn_mfp, dsi_dn0_mfp, 66 dsi_dp2_mfp, lcd0_d2_mfp, dsi_dp3_mfp, dsi_dn3_mfp, dsi_dp0_mfp, 67 lvds_ee_pn_mfp, uart2_rx_tx_mfp, spi0_i2c_pcm_mfp, 68 dsi_dnp1_cp_d2_mfp, dsi_dnp1_cp_d17_mfp, lvds_e_pn_mfp, 69 dsi_dn2_mfp, uart2_rtsb_mfp, uart2_ctsb_mfp, uart3_rtsb_mfp, 70 uart3_ctsb_mfp, sd0_d0_mfp, sd0_d1_mfp, sd0_d2_d3_mfp, 71 sd1_d0_d3_mfp, sd0_cmd_mfp, sd0_clk_mfp, sd1_cmd_mfp, 72 uart0_rx_mfp, clko_25m_mfp, csi_cn_cp_mfp, sens0_ckout_mfp, 73 uart0_tx_mfp, i2c0_mfp, csi_dn_dp_mfp, sen0_pclk_mfp, pcm1_in_mfp, 74 pcm1_clk_mfp, pcm1_sync_mfp, pcm1_out_mfp, dnand_data_wr_mfp, 75 dnand_acle_ce0_mfp, nand_ceb2_mfp, nand_ceb3_mfp 76 ] 77 78 function: 79 items: 80 enum: [ 81 nor, eth_rgmii, eth_sgmii, spi0, spi1, spi2, spi3, seNs0, sens1, 82 uart0, uart1, uart2, uart3, uart4, uart5, uart6, i2s0, i2s1, pcm1, 83 pcm0, ks, jtag, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, p0, sd0, sd1, 84 sd2, i2c0, i2c1, i2c2, i2c3, dsi, lvds, usb30, clko_25m, mipi_csi, 85 nand, spdif, sirq0, sirq1, sirq2, bt, lcd0 86 ] 87 88 required: 89 - groups 90 - function 91 92 pinconf: 93 description: Configure pin-specific parameters. 94 type: object 95 allOf: 96 - $ref: /schemas/pinctrl/pincfg-node.yaml# 97 - $ref: /schemas/pinctrl/pinmux-node.yaml# 98 additionalProperties: false 99 100 properties: 101 groups: 102 items: 103 enum: [ 104 sirq_drv, rgmii_txd23_drv, rgmii_rxd23_drv, rgmii_txd01_txen_drv, 105 rgmii_rxer_drv, rgmii_crs_drv, rgmii_rxd10_drv, rgmii_ref_clk_drv, 106 smi_mdc_mdio_drv, i2s_d0_drv, i2s_bclk0_drv, i2s3_drv, i2s13_drv, 107 pcm1_drv, ks_in_drv, ks_out_drv, lvds_all_drv, lcd_d18_d2_drv, 108 dsi_all_drv, sd0_d0_d3_drv, sd0_cmd_drv, sd0_clk_drv, 109 spi0_all_drv, uart0_rx_drv, uart0_tx_drv, uart2_all_drv, 110 i2c0_all_drv, i2c12_all_drv, sens0_pclk_drv, sens0_ckout_drv, 111 uart3_all_drv 112 ] 113 114 pins: 115 items: 116 enum: [ 117 eth_txd0, eth_txd1, eth_txd2, eth_txd3, eth_txen, eth_rxer, 118 eth_crs_dv, eth_rxd1, eth_rxd0, eth_rxd2, eth_rxd3, eth_ref_clk, 119 eth_mdc, eth_mdio, sirq0, sirq1, sirq2, i2s_d0, i2s_bclk0, 120 i2s_lrclk0, i2s_mclk0, i2s_d1, i2s_bclk1, i2s_lrclk1, i2s_mclk1, 121 pcm1_in, pcm1_clk, pcm1_sync, pcm1_out, ks_in0, ks_in1, ks_in2, 122 ks_in3, ks_out0, ks_out1, ks_out2, lvds_oep, lvds_oen, lvds_odp, 123 lvds_odn, lvds_ocp, lvds_ocn, lvds_obp, lvds_obn, lvds_oap, 124 lvds_oan, lvds_eep, lvds_een, lvds_edp, lvds_edn, lvds_ecp, 125 lvds_ecn, lvds_ebp, lvds_ebn, lvds_eap, lvds_ean, lcd0_d18, 126 lcd0_d2, dsi_dp3, dsi_dn3, dsi_dp1, dsi_dn1, dsi_cp, dsi_cn, 127 dsi_dp0, dsi_dn0, dsi_dp2, dsi_dn2, sd0_d0, sd0_d1, sd0_d2, 128 sd0_d3, sd1_d0, sd1_d1, sd1_d2, sd1_d3, sd0_cmd, sd0_clk, sd1_cmd, 129 sd1_clk, spi0_ss, spi0_miso, uart0_rx, uart0_tx, uart2_rx, 130 uart2_tx, uart2_rtsb, uart2_ctsb, uart3_rx, uart3_tx, uart3_rtsb, 131 uart3_ctsb, i2c0_sclk, i2c0_sdata, i2c1_sclk, i2c1_sdata, 132 i2c2_sclk, i2c2_sdata, csi_dn0, csi_dp0, csi_dn1, csi_dp1, csi_cn, csi_cp, 133 csi_dn2, csi_dp2, csi_dn3, csi_dp3, sensor0_pclk, sensor0_ckout, 134 dnand_d0, dnand_d1, dnand_d2, dnand_d3, dnand_d4, dnand_d5, 135 dnand_d6, dnand_d7, dnand_wrb, dnand_rdb, dnand_rdbn, dnand_dqs, 136 dnand_dqsn, dnand_rb0, dnand_ale, dnand_cle, dnand_ceb0, 137 dnand_ceb1, dnand_ceb2, dnand_ceb3, porb, clko_25m, bsel, pkg0, 138 pkg1, pkg2, pkg3 139 ] 140 141 bias-pull-down: 142 type: boolean 143 144 bias-pull-up: 145 type: boolean 146 147 drive-strength: 148 description: Selects the drive strength for the specified pins in mA. 149 enum: [2, 4, 8, 12] 150 151 input-schmitt-enable: true 152 input-schmitt-disable: true 153 154 oneOf: 155 - required: 156 - groups 157 - required: 158 - pins 159 160 anyOf: 161 - required: [ pinmux ] 162 - required: [ pinconf ] 163 164required: 165 - compatible 166 - reg 167 - clocks 168 - gpio-controller 169 - gpio-ranges 170 - '#gpio-cells' 171 - interrupt-controller 172 - '#interrupt-cells' 173 - interrupts 174 175examples: 176 - | 177 #include <dt-bindings/interrupt-controller/arm-gic.h> 178 179 pinctrl: pinctrl@e01b0000 { 180 compatible = "actions,s700-pinctrl"; 181 reg = <0xe01b0000 0x1000>; 182 clocks = <&cmu 1>; 183 gpio-controller; 184 gpio-ranges = <&pinctrl 0 0 136>; 185 #gpio-cells = <2>; 186 interrupt-controller; 187 #interrupt-cells = <2>; 188 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 193 194 uart3-default { 195 pinmux { 196 groups = "uart3_rtsb_mfp", "uart3_ctsb_mfp"; 197 function = "uart3"; 198 }; 199 pinconf { 200 groups = "uart3_all_drv"; 201 drive-strength = <2>; 202 }; 203 }; 204 }; 205