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/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dqca,ar71xx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: ethernet-controller.yaml#
13 - Oleksij Rempel <o.rempel@pengutronix.de>
18 - items:
19 - enum:
20 - qca,ar7100-eth # Atheros AR7100
21 - qca,ar7240-eth # Atheros AR7240
22 - qca,ar7241-eth # Atheros AR7241
[all …]
H A Dmediatek-net.txt10 - compatible: Should be
11 "mediatek,mt2701-eth": for MT2701 SoC
12 "mediatek,mt7623-eth", "mediatek,mt2701-eth": for MT7623 SoC
13 "mediatek,mt7622-eth": for MT7622 SoC
14 "mediatek,mt7629-eth": for MT7629 SoC
15 "ralink,rt5350-eth": for Ralink Rt5350F and MT7628/88 SoC
16 - reg: Address and length of the register set for the device
17 - interrupts: Should contain the three frame engines interrupts in numeric
19 - clocks: the clock used by the core
20 - clock-names: the names of the clock listed in the clocks property. These are
[all …]
H A Dmediatek,net.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Bianconi <lorenzo@kernel.org>
11 - Felix Fietkau <nbd@nbd.name>
20 - mediatek,mt2701-eth
21 - mediatek,mt7623-eth
22 - mediatek,mt7621-eth
23 - mediatek,mt7622-eth
24 - mediatek,mt7629-eth
[all …]
H A Dralink,rt2880-net.txt8 directly and/or via a (gigabit-)switch.
13 - compatible: Should be one of "ralink,rt2880-eth", "ralink,rt3050-eth",
14 "ralink,rt3050-eth", "ralink,rt3883-eth", "ralink,rt5350-eth",
15 "mediatek,mt7620-eth", "mediatek,mt7621-eth"
16 - reg: Address and length of the register set for the device
17 - interrupts: Should contain the frame engines interrupt
18 - resets: Should contain the frame engines resets
19 - reset-names: Should contain the reset names "fe". If a switch is present
26 - compatible: Should be "ralink,eth-port"
27 - reg: The number of the physical port
[all …]
H A Dmarvell-orion-net.txt12 set of controller registers. Each port node describes port-specific properties.
16 only one port associated. Multiple ports are implemented as multiple single-port
23 - #address-cells: shall be 1.
24 - #size-cells: shall be 0.
25 - compatible: shall be one of "marvell,orion-eth", "marvell,kirkwood-eth".
26 - reg: address and length of the controller registers.
29 - clocks: phandle reference to the controller clock.
30 - marvell,tx-checksum-limit: max tx packet size for hardware checksum.
35 - compatible: shall be one of "marvell,orion-eth-port",
36 "marvell,kirkwood-eth-port".
[all …]
H A Dcirrus,ep9301-eth.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/cirrus,ep9301-eth.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexander Sverdlin <alexander.sverdlin@gmail.com>
11 - Nikita Shubin <nikita.shubin@maquefel.me>
14 - $ref: ethernet-controller.yaml#
19 - const: cirrus,ep9301-eth
20 - items:
21 - enum:
[all …]
H A Dmediatek,star-emac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/mediatek,star-emac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bartosz Golaszewski <bgolaszewski@baylibre.com>
14 It's compliant with 802.3 standards and supports half- and full-duplex
15 modes with flow-control as well as CRC offloading and VLAN tags.
18 - $ref: ethernet-controller.yaml#
23 - mediatek,mt8516-eth
24 - mediatek,mt8518-eth
[all …]
H A Dstm32-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/stm32-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Alexandre Torgue <alexandre.torgue@foss.st.com>
12 - Christophe Roullier <christophe.roullier@foss.st.com>
23 - st,stm32-dwmac
24 - st,stm32mp1-dwmac
25 - st,stm32mp13-dwmac
26 - st,stm32mp25-dwmac
[all …]
H A Dlpc-eth.txt4 - compatible: Should be "nxp,lpc-eth"
5 - reg: Address and length of the register set for the device
6 - interrupts: Should contain ethernet controller interrupt
9 - phy-mode: See ethernet.txt file in the same directory. If the property is
11 - use-iram: Use LPC32xx internal SRAM (IRAM) for DMA buffering
14 - mdio : specifies the mdio bus, used as a container for phy nodes according to
15 phy.txt in the same directory
21 compatible = "nxp,lpc-eth";
23 interrupt-parent = <&mic>;
26 phy-mode = "rmii";
[all …]
H A Dmarvell-pxa168.txt4 - compatible: should be "marvell,pxa168-eth".
5 - reg: address and length of the register set for the device.
6 - interrupts: interrupt for the device.
7 - clocks: pointer to the clock for the device.
10 - port-id: Ethernet port number. Should be '0','1' or '2'.
11 - #address-cells: must be 1 when using sub-nodes.
12 - #size-cells: must be 0 when using sub-nodes.
13 - phy-handle: see ethernet.txt file in the same directory.
18 Sub-nodes:
19 Each PHY can be represented as a sub-node. This is not mandatory.
[all …]
H A Dactions,owl-emac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/actions,owl-emac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
15 IEEE 802.3 CSMA/CD standard, supporting both half-duplex and full-duplex
19 - $ref: ethernet-controller.yaml#
24 - const: actions,owl-emac
25 - items:
26 - enum:
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/rockchip/
H A Drk3568-wolfvision-pf5-io-expander.dtso1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
8 /dts-v1/;
11 #include <dt-bindings/clock/rk3568-cru.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/pinctrl/rockchip.h>
17 gmac0_clkin: external-gmac0-clock {
18 compatible = "fixed-clock";
19 clock-frequency = <50000000>;
20 clock-output-names = "gmac0_clkin";
[all …]
H A Drk3568-fastrhino-r68s.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 #include "rk3568-fastrhino-r66s.dtsi"
7 compatible = "lunzn,fastrhino-r68s", "rockchip,rk3568";
15 adc-keys {
16 compatible = "adc-keys";
17 io-channels = <&saradc 0>;
18 io-channel-names = "buttons";
19 keyup-threshold-microvolt = <1800000>;
21 button-recovery {
24 press-threshold-microvolt = <1750>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/amlogic/
H A Dmeson-gxbb-odroidc2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "meson-gxbb.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/sound/meson-aiu.h>
15 compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb";
16 model = "Hardkernel ODROID-C2";
24 stdout-path = "serial0:115200n8";
32 usb_otg_pwr: regulator-usb-pwrs {
33 compatible = "regulator-fixed";
[all …]
H A Dmeson-gxbb-nanopi-k2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "meson-gxbb.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/sound/meson-aiu.h>
13 compatible = "friendlyarm,nanopi-k2", "amlogic,meson-gxbb";
22 stdout-path = "serial0:115200n8";
31 compatible = "gpio-leds";
33 led-stat {
34 label = "nanopi-k2:blue:stat";
[all …]
/freebsd/sys/contrib/device-tree/Bindings/net/dsa/
H A Dar9331.txt1 Atheros AR9331 built-in switch
4 It is a switch built-in to Atheros AR9331 WiSoC and addressable over internal
5 MDIO bus. All PHYs are built-in as well.
9 - compatible: should be: "qca,ar9331-switch"
10 - reg: Address on the MII bus for the switch.
11 - resets : Must contain an entry for each entry in reset-names.
12 - reset-names : Must include the following entries: "switch"
13 - interrupt-parent: Phandle to the parent interrupt controller
14 - interrupts: IRQ line for the switch
15 - interrupt-controller: Indicates the switch is itself an interrupt
[all …]
H A Dmt7530.txt6 - compatible: may be compatible = "mediatek,mt7530"
9 - #address-cells: Must be 1.
10 - #size-cells: Must be 0.
11 - mediatek,mcm: Boolean; if defined, indicates that either MT7530 is the part
12 on multi-chip module belong to MT7623A has or the remotely standalone
17 - core-supply: Phandle to the regulator node necessary for the core power.
18 - io-supply: Phandle to the regulator node necessary for the I/O power.
19 See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt
24 - reset-gpios: Should be a gpio specifier for a reset line.
28 - resets : Phandle pointing to the system reset controller with
[all …]
/freebsd/sys/contrib/device-tree/src/mips/qca/
H A Dar9331.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ath79-clk.h>
7 #address-cells = <1>;
8 #size-cells = <1>;
11 #address-cells = <1>;
12 #size-cells = <0>;
22 cpuintc: interrupt-controller {
23 compatible = "qca,ar7100-cpu-intc";
25 interrupt-controller;
26 #interrupt-cells = <1>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/mediatek/
H A Dmt7629-rfb.dts1 // SPDX-License-Identifier: GPL-2.0
7 /dts-v1/;
8 #include <dt-bindings/input/input.h>
13 compatible = "mediatek,mt7629-rfb", "mediatek,mt7629";
20 stdout-path = "serial0:115200n8";
23 gpio-keys {
24 compatible = "gpio-keys";
26 button-rese
[all...]
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dkmeter1.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * 2008-2011 DENX Software Engineering GmbH
8 /dts-v1/;
13 #address-cells = <1>;
14 #size-cells = <1>;
28 #address-cells = <1>;
29 #size-cells = <0>;
34 d-cache-line-size = <32>; // 32 bytes
35 i-cache-line-size = <32>; // 32 bytes
36 d-cache-size = <32768>; // L1, 32K
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-am654-idk.dtso1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti.com/
8 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/net/ti-dp83867.h>
13 #include "k3-pinctrl.h"
17 ethernet3 = "/icssg0-eth/ethernet-ports/port@0";
18 ethernet4 = "/icssg0-eth/ethernet-ports/port@1";
19 ethernet5 = "/icssg1-eth/ethernet-ports/port@0";
20 ethernet6 = "/icssg1-eth/ethernet-ports/port@1";
[all …]
H A Dk3-am654-icssg2.dtso1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti.com/
8 /dts-v1/;
11 #include <dt-bindings/net/ti-dp83867.h>
12 #include "k3-pinctrl.h"
16 ethernet1 = "/icssg2-eth/ethernet-ports/port@0";
17 ethernet2 = "/icssg2-eth/ethernet-ports/port@1";
20 /* Ethernet node on PRU-ICSSG2 */
21 icssg2_eth: icssg2-eth {
22 compatible = "ti,am654-icssg-prueth";
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt7986b-rfb.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
12 chassis-type = "embedded";
13 compatible = "mediatek,mt7986b-rfb", "mediatek,mt7986b";
20 stdout-path = "serial0:115200n8";
33 &eth {
37 compatible = "mediatek,eth-mac";
39 phy-mode = "2500base-x";
41 fixed-link {
43 full-duplex;
[all …]
H A Dmt2712-evb.dts5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
14 chassis-type = "embedded";
15 compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
27 stdout-path = "serial0:921600n8";
30 cpus_fixed_vproc0: regulator-vproc-buck0 {
31 compatible = "regulator-fixed";
32 regulator-name = "vproc_buck0";
33 regulator-min-microvolt = <1000000>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/marvell/
H A Dkirkwood.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/input/input.h>
3 #include <dt-bindings/gpio/gpio.h>
8 #address-cells = <1>;
9 #size-cells = <1>;
11 interrupt-parent = <&intc>;
14 #address-cells = <1>;
15 #size-cells = <0>;
22 clock-names = "cpu_clk", "ddrclk", "powersave";
33 compatible = "marvell,kirkwood-mbus", "simple-bus";
[all …]

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