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/linux/arch/arm64/boot/dts/arm/
H A Dfvp-base-revc.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Architecture Envelope Model (AEM) ARMv8-A
11 /dts-v1/;
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include "rtsm_ve-motherboard.dtsi"
18 #include "rtsm_ve-motherboard-rs2.dtsi"
22 compatible = "arm,fvp-base-revc", "arm,vexpress";
23 interrupt-parent = <&gic>;
24 #address-cells = <2>;
25 #size-cells = <2>;
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/linux/tools/perf/util/cs-etm-decoder/
H A Dcs-etm-decoder.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright(C) 2015-2018 Linaro Limited.
10 #include <linux/coresight-pmu.h>
17 #include "cs-etm.h"
18 #include "cs-etm-decoder.h"
35 * case with a theoretical 10GHz core executing 1 instruction per cycle.
62 return decoder->mem_access(decoder->data, trace_chan_id, address, in cs_etm_decoder__mem_access()
70 decoder->mem_access = cb_func; in cs_etm_decoder__add_mem_access_cb()
72 if (ocsd_dt_add_callback_trcid_mem_acc(decoder->dcd_tree, start, end, in cs_etm_decoder__add_mem_access_cb()
76 return -1; in cs_etm_decoder__add_mem_access_cb()
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H A Dcs-etm-decoder.h2 * SPDX-License-Identifier: GPL-2.0
4 * Copyright(C) 2015-2018 Linaro Limited.
57 struct cs_ete_trace_params ete; member
73 * The following enums are indexed starting with 1 to align with the
77 CS_ETM_PROTO_ETMV3 = 1,
85 CS_ETM_OPERATION_PRINT = 1,
/linux/tools/perf/arch/arm/util/
H A Dcs-etm.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/coresight-pmu.h>
18 #include "cs-etm.h"
29 #include "../../../util/cs-etm.h"
93 u64 contextid = evsel->core.attr.config & in cs_etm_validate_context_id()
105 return -EINVAL; in cs_etm_validate_context_id()
116 * TRCIDR2.CIDSIZE, bit [9-5], indicates whether contextID in cs_etm_validate_context_id()
119 * 0b00100 Maximum of 32-bit Context ID size. in cs_etm_validate_context_id()
125 return -EINVAL; in cs_etm_validate_context_id()
141 return -EINVAL; in cs_etm_validate_context_id()
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/linux/drivers/hwtracing/coresight/
H A Dcoresight-trbe.c1 // SPDX-License-Identifier: GPL-2.0
3 * This driver enables Trace Buffer Extension (TRBE) as a per-cpu coresight
4 * sink device could then pair with an appropriate per-cpu coresight source
5 * device (ETE) thus generating required trace data. Trace can be enabled
23 #include "coresight-self-hosted-trace.h"
24 #include "coresight-trbe.h"
27 ((idx) % ((unsigned long)(buf)->nr_pages << PAGE_SHIFT))
34 * sinks and thus we use ETE trace packets to pad the
41 * A-Sync, Trace Info, Trace On, Address, Atom.
42 * This is about 44bytes of ETE trace. To be on
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H A Dcoresight-etm4x-core.c1 // SPDX-License-Identifier: GPL-2.0
27 #include <linux/coresight-pmu.h>
35 #include <linux/clk/clk-conf.h>
43 #include "coresight-etm4x.h"
44 #include "coresight-etm-perf.h"
45 #include "coresight-etm4x-cfg.h"
46 #include "coresight-self-hosted-trace.h"
47 #include "coresight-syscfg.h"
48 #include "coresight-trace-id.h"
54 #define PARAM_PM_SAVE_FIRMWARE 0 /* save self-hosted state as per firmware */
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H A Dcoresight-platform.c1 // SPDX-License-Identifier: GPL-2.0
19 #include "coresight-priv.h"
24 * If the output port is already assigned on this device, return -EINVAL
37 for (i = 0; i < pdata->nr_outconns; ++i) { in coresight_add_out_conn()
38 conn = pdata->out_conns[i]; in coresight_add_out_conn()
39 /* Output == -1 means ignore the port for example for helpers */ in coresight_add_out_conn()
40 if (conn->src_port != -1 && in coresight_add_out_conn()
41 conn->src_port == new_conn->src_port) { in coresight_add_out_conn()
43 conn->src_port); in coresight_add_out_conn()
44 return ERR_PTR(-EINVAL); in coresight_add_out_conn()
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H A Dcoresight-etm4x.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
13 #include "coresight-priv.h"
17 * 0x000 - 0x2FC: Trace registers
18 * 0x300 - 0x314: Management registers
19 * 0x318 - 0xEFC: Trace registers
21 * 0xFA0 - 0xFA4: Trace registers
22 * 0xFA8 - 0xFFC: Management registers
24 /* Trace registers (0x000-0x2FC) */
47 #define TRCSEQEVRn(n) (0x100 + (n * 4)) /* n = 0-2 */
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/linux/tools/perf/util/
H A Dcs-etm.h1 /* SPDX-License-Identifier: GPL-2.0 */
24 /* PMU->type (32 bit), total # of CPUs (32 bit) */
33 * Version 1: format adds a param count to the per cpu metadata.
65 /* define fixed version 0 length - allow new format reader to read old files. */
66 #define CS_ETM_NR_TRC_PARAMS_V0 (CS_ETM_ETMIDR - CS_ETM_ETMCR + 1)
83 /* define fixed version 0 length - allow new format reader to read old files. */
84 #define CS_ETMV4_NR_TRC_PARAMS_V0 (CS_ETMV4_TRCAUTHSTATUS - CS_ETMV4_TRCCONFIGR + 1)
87 * ETE metadata is ETMv4 plus TRCDEVARCH register and doesn't support header V0 since it was
114 * table 7-12 Encoding of Exception[3:0] for non-ARMv7-M processors.
118 CS_ETMV3_EXC_DEBUG_HALT = 1,
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H A Dcs-etm.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright(C) 2015-2018 Linaro Limited.
12 #include <linux/coresight-pmu.h>
22 #include "cs-etm.h"
23 #include "cs-etm-decoder/cs-etm-decoder.h"
37 #include "thread-stack.h"
40 #include "util/synthetic-events.h"
61 * Per-thread ignores the trace channel ID and instead assumes that
151 #define SINK_UNSET ((u32) -1)
168 inode = intlist__find(etmq->traceid_list, trace_chan_id); in cs_etm__get_magic()
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/linux/arch/m68k/fpsp040/
H A Dget_op.S7 | type exception handler ('unsupp' - vector 55) and the unimplemented
8 | instruction exception handler ('unimp' - vector 11). 'get_op'
10 | opclass handler routine. See 68881/2 User's Manual table 4-11
17 | - For unnormalized numbers (opclass 0, 2, or 3) the
20 | - For a packed number (opclass 2) the number is unpacked and the
23 | - For denormalized numbers (opclass 0 or 2) the number(s) is not
30 | - If there is a move out with a packed number (opclass 3) the
41 | the '040. The '040 then re-executes the fadd.x fpm,fpn with
45 | Next consider if in the process of normalizing the un-
60 GET_OP: |idnt 2,1 | Motorola 040 Floating Point Software Package
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/linux/Documentation/trace/coresight/
H A Dpanic.rst6 ------------
11 -----------------------------------
27 A new optional device tree property "memory-region" is added to the
53 Comparator --->External out --->CTI -->External In---->ETR/ETF stop
61 A new optional device property "memory-region" is added to
72 1. Enable source and sink on all the cores using the sysfs interface.
93 -------------------------------------
110 -------------------------------------------------------------
112 1. Boot Linux kernel with "crash_kexec_post_notifiers" added to the kernel
118 #echo 1 > /sys/kernel/config/cs-syscfg/configurations/panicstop/enable
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/linux/arch/arm64/boot/dts/qcom/
H A Dsm8450.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
8 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
9 #include <dt-bindings/clock/qcom,rpmh.h>
10 #include <dt-bindings/clock/qcom,sm8450-camcc.h>
11 #include <dt-bindings/clock/qcom,sm8450-dispcc.h>
12 #include <dt-bindings/clock/qcom,sm8450-gpucc.h>
13 #include <dt-bindings/clock/qcom,sm8450-videocc.h>
14 #include <dt-bindings/dma/qcom-gpi.h>
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H A Dsm8650.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
7 #include <dt-bindings/clock/qcom,rpmh.h>
8 #include <dt-bindings/clock/qcom,sm8650-camcc.h>
9 #include <dt-bindings/clock/qcom,sm8650-dispcc.h>
10 #include <dt-bindings/clock/qcom,sm8650-gcc.h>
11 #include <dt-bindings/clock/qcom,sm8650-gpucc.h>
12 #include <dt-bindings/clock/qcom,sm8650-tcsr.h>
13 #include <dt-bindings/clock/qcom,sm8650-videocc.h>
14 #include <dt-bindings/dma/qcom-gpi.h>
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/linux/drivers/usb/cdns3/
H A Dcdnsp-gadget.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 #include <linux/io-64-nonatomic-lo-hi.h>
19 /* Max number slots - only 1 is allowed. */
20 #define CDNSP_DEV_MAX_SLOTS 1
43 * struct cdnsp_cap_regs - CDNSP Registers.
46 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1
47 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2
48 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3
49 * @hcc_params: HCCPARAMS - Capability Parameters
50 * @db_off: DBOFF - Doorbell array offset
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/linux/drivers/usb/host/
H A Dxhci.h1 /* SPDX-License-Identifier: GPL-2.0 */
19 #include <linux/io-64-nonatomic-lo-hi.h>
20 #include <linux/io-64-nonatomic-hi-lo.h>
22 /* Code sharing between pci-quirks and xhci hcd */
23 #include "xhci-ext-caps.h"
24 #include "pci-quirks.h"
26 #include "xhci-port.h"
27 #include "xhci-caps.h"
35 /* Max number of USB devices for any host controller - limit in section 6.1 */
39 * Valid values are in the range of 1 to 255.
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H A Dxhci-ring.c1 // SPDX-License-Identifier: GPL-2.0
13 * 1. Each segment is initialized to zero, except for link TRBs.
19 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
26 * until you reach a non-link TRB.
31 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
37 * 1. Check if ring is full before you enqueue.
46 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 #include <linux/dma-mapping.h>
61 #include "xhci-trace.h"
76 if (!seg || !trb || trb < seg->trbs) in xhci_trb_virt_to_dma()
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