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Searched full:esync (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/dpll/zl3073x/
H A Ddpll.c58 * Supported esync ranges for input and for output per output pair type
160 struct dpll_pin_esync *esync, in zl3073x_dpll_input_pin_esync_get() argument
189 /* Get esync divisor */ in zl3073x_dpll_input_pin_esync_get()
198 esync->freq = (esync_div == ZL_REF_ESYNC_DIV_1HZ) ? 1 : 0; in zl3073x_dpll_input_pin_esync_get()
199 esync->pulse = 25; in zl3073x_dpll_input_pin_esync_get()
202 esync->freq = 0; in zl3073x_dpll_input_pin_esync_get()
203 esync->pulse = 0; in zl3073x_dpll_input_pin_esync_get()
207 /* If the pin supports esync control expose its range but only in zl3073x_dpll_input_pin_esync_get()
211 esync->range = esync_freq_ranges; in zl3073x_dpll_input_pin_esync_get()
212 esync->range_num = ARRAY_SIZE(esync_freq_ranges); in zl3073x_dpll_input_pin_esync_get()
[all …]
H A Dprop.c180 * board label, connection type, supported frequencies and esync capability
249 "esync-control"); in zl3073x_pin_props_get()
/linux/Documentation/netlink/specs/
H A Ddpll.yaml412 name: esync-frequency
418 name: esync-frequency-supported
426 name: esync-pulse
615 - esync-frequency
616 - esync-frequency-supported
617 - esync-pulse
645 - esync-frequency
/linux/drivers/dpll/
H A Ddpll_netlink.c410 struct dpll_pin_esync esync; in dpll_msg_add_pin_esync() local
417 dpll_priv(dpll), &esync, extack); in dpll_msg_add_pin_esync()
422 if (nla_put_64bit(msg, DPLL_A_PIN_ESYNC_FREQUENCY, sizeof(esync.freq), in dpll_msg_add_pin_esync()
423 &esync.freq, DPLL_A_PIN_PAD)) in dpll_msg_add_pin_esync()
425 if (nla_put_u32(msg, DPLL_A_PIN_ESYNC_PULSE, esync.pulse)) in dpll_msg_add_pin_esync()
427 for (i = 0; i < esync.range_num; i++) { in dpll_msg_add_pin_esync()
433 sizeof(esync.range[i].min), in dpll_msg_add_pin_esync()
434 &esync.range[i].min, DPLL_A_PIN_PAD)) in dpll_msg_add_pin_esync()
437 sizeof(esync.range[i].max), in dpll_msg_add_pin_esync()
438 &esync.range[i].max, DPLL_A_PIN_PAD)) in dpll_msg_add_pin_esync()
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/linux/Documentation/devicetree/bindings/dpll/
H A Dmicrochip,zl30731.yaml70 esync-control;
108 esync-control;
H A Ddpll-pin.yaml31 esync-control:
/linux/drivers/net/ethernet/intel/ice/
H A Dice_dpll.c1906 * @esync: on success holds embedded sync pin properties
1920 struct dpll_pin_esync *esync, in ice_dpll_output_esync_get() argument
1935 esync->range = ice_esync_range; in ice_dpll_output_esync_get()
1936 esync->range_num = ARRAY_SIZE(ice_esync_range); in ice_dpll_output_esync_get()
1938 esync->freq = DPLL_PIN_FREQUENCY_1_HZ; in ice_dpll_output_esync_get()
1939 esync->pulse = ICE_DPLL_PIN_ESYNC_PULSE_HIGH_PERCENT; in ice_dpll_output_esync_get()
1941 esync->freq = 0; in ice_dpll_output_esync_get()
1942 esync->pulse = 0; in ice_dpll_output_esync_get()
2010 * @esync: on success holds embedded sync pin properties
2024 struct dpll_pin_esync *esync, in ice_dpll_input_esync_get() argument
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/linux/include/linux/
H A Ddpll.h104 struct dpll_pin_esync *esync,
/linux/arch/xtensa/kernel/
H A Dentry.S1714 esync
1887 esync
/linux/sound/pci/echoaudio/
H A Dechoaudio.c1537 "Internal", "Word", "Super", "S/PDIF", "ADAT", "ESync", in snd_echo_clock_source_info()
/linux/arch/powerpc/xmon/
H A Dppc-opc.c687 /* The ESYNC field in an X (sync) form instruction. */
688 #define ESYNC STRM + 1 macro
692 #define SV ESYNC + 1
1529 If ESYNC is non-zero, then the L field must be either 0 or 1 and
1530 the complement of ESYNC-bit2. */
5848 {"sync", X(31,598), XSYNCLE_MASK, E6500, 0, {LS, ESYNC}},