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123

/freebsd/sys/dev/sfxge/common/
H A Defx_mac.c99 efx_port_t *epp = &(enp->en_port); in efx_mac_pdu_set() local
100 const efx_mac_ops_t *emop = epp->ep_emop; in efx_mac_pdu_set()
118 old_pdu = epp->ep_mac_pdu; in efx_mac_pdu_set()
119 epp->ep_mac_pdu = (uint32_t)pdu; in efx_mac_pdu_set()
128 epp->ep_mac_pdu = old_pdu; in efx_mac_pdu_set()
143 efx_port_t *epp = &(enp->en_port); in efx_mac_pdu_get() local
144 const efx_mac_ops_t *emop = epp->ep_emop; in efx_mac_pdu_get()
163 efx_port_t *epp = &(enp->en_port); in efx_mac_addr_set() local
164 const efx_mac_ops_t *emop = epp->ep_emop; in efx_mac_addr_set()
183 EFX_MAC_ADDR_COPY(old_addr, epp->ep_mac_addr); in efx_mac_addr_set()
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H A Defx_phy.c81 efx_port_t *epp = &(enp->en_port); in efx_phy_probe() local
88 epp->ep_port = encp->enc_port; in efx_phy_probe()
89 epp->ep_phy_type = encp->enc_phy_type; in efx_phy_probe()
122 epp->ep_epop = epop; in efx_phy_probe()
129 epp->ep_port = 0; in efx_phy_probe()
130 epp->ep_phy_type = 0; in efx_phy_probe()
139 efx_port_t *epp = &(enp->en_port); in efx_phy_verify() local
140 const efx_phy_ops_t *epop = epp->ep_epop; in efx_phy_verify()
156 efx_port_t *epp = &(enp->en_port); in efx_phy_led_set() local
157 const efx_phy_ops_t *epop = epp->ep_epop; in efx_phy_led_set()
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H A Defx_port.c41 efx_port_t *epp = &(enp->en_port); in efx_port_init() local
42 const efx_phy_ops_t *epop = epp->ep_epop; in efx_port_init()
56 epp->ep_mac_type = EFX_MAC_INVALID; in efx_port_init()
57 epp->ep_link_mode = EFX_LINK_UNKNOWN; in efx_port_init()
58 epp->ep_mac_drain = B_TRUE; in efx_port_init()
64 epp->ep_emop->emo_reconfigure(enp); in efx_port_init()
106 efx_port_t *epp = &(enp->en_port); in efx_port_poll() local
107 const efx_mac_ops_t *emop = epp->ep_emop; in efx_port_poll()
138 efx_port_t *epp = &(enp->en_port); in efx_port_loopback_set() local
140 const efx_mac_ops_t *emop = epp->ep_emop; in efx_port_loopback_set()
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H A Def10_mac.c42 efx_port_t *epp = &(enp->en_port); in ef10_mac_poll() local
49 epp->ep_adv_cap_mask = els.epls.epls_adv_cap_mask; in ef10_mac_poll()
50 epp->ep_fcntl = els.epls.epls_fcntl; in ef10_mac_poll()
74 * ef10_mac_poll() being executed to populate epp->ep_mac_up. in ef10_mac_up()
100 efx_port_t *epp = &(enp->en_port); in efx_mcdi_vadapter_set_mac() local
115 epp->ep_mac_addr); in efx_mcdi_vadapter_set_mac()
247 efx_port_t *epp = &(enp->en_port); in ef10_mac_pdu_set() local
252 if ((rc = efx_mcdi_mtu_set(enp, epp->ep_mac_pdu)) != 0) in ef10_mac_pdu_set()
296 efx_port_t *epp = &(enp->en_port); in ef10_mac_reconfigure() local
308 MCDI_IN_SET_DWORD(req, SET_MAC_IN_MTU, epp->ep_mac_pdu); in ef10_mac_reconfigure()
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H A Dsiena_mac.c44 efx_port_t *epp = &(enp->en_port); in siena_mac_poll() local
51 epp->ep_adv_cap_mask = sls.sls_adv_cap_mask; in siena_mac_poll()
52 epp->ep_fcntl = sls.sls_fcntl; in siena_mac_poll()
76 * siena_mac_poll() being executed to populate epp->ep_mac_up. in siena_mac_up()
95 efx_port_t *epp = &(enp->en_port); in siena_mac_reconfigure() local
111 MCDI_IN_SET_DWORD(req, SET_MAC_IN_MTU, epp->ep_mac_pdu); in siena_mac_reconfigure()
112 MCDI_IN_SET_DWORD(req, SET_MAC_IN_DRAIN, epp->ep_mac_drain ? 1 : 0); in siena_mac_reconfigure()
114 epp->ep_mac_addr); in siena_mac_reconfigure()
116 SET_MAC_IN_REJECT_UNCST, !epp->ep_all_unicst, in siena_mac_reconfigure()
117 SET_MAC_IN_REJECT_BRDCST, !epp->ep_brdcst); in siena_mac_reconfigure()
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H A Dsiena_phy.c118 efx_port_t *epp = &(enp->en_port); in siena_phy_link_ev() local
162 epp->ep_lp_cap_mask = lp_cap_mask; in siena_phy_link_ev()
163 if (epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_AN)) in siena_phy_link_ev()
164 epp->ep_fcntl = fcntl; in siena_phy_link_ev()
271 efx_port_t *epp = &(enp->en_port); in siena_phy_reconfigure() local
289 cap_mask = epp->ep_adv_cap_mask; in siena_phy_reconfigure()
304 epp->ep_loopback_type); in siena_phy_reconfigure()
305 switch (epp->ep_loopback_link_mode) { in siena_phy_reconfigure()
325 MCDI_IN_SET_DWORD(req, SET_LINK_IN_FLAGS, epp->ep_phy_flags); in siena_phy_reconfigure()
346 switch (epp->ep_phy_led_mode) { in siena_phy_reconfigure()
H A Def10_phy.c195 efx_port_t *epp = &(enp->en_port); in ef10_phy_link_ev() local
253 epp->ep_lp_cap_mask = lp_cap_mask; in ef10_phy_link_ev()
254 epp->ep_fcntl = fcntl; in ef10_phy_link_ev()
359 efx_port_t *epp = &(enp->en_port); in ef10_phy_reconfigure() local
382 cap_mask = epp->ep_adv_cap_mask; in ef10_phy_reconfigure()
425 epp->ep_loopback_type); in ef10_phy_reconfigure()
426 switch (epp->ep_loopback_link_mode) { in ef10_phy_reconfigure()
458 MCDI_IN_SET_DWORD(req, SET_LINK_IN_FLAGS, epp->ep_phy_flags); in ef10_phy_reconfigure()
479 switch (epp->ep_phy_led_mode) { in ef10_phy_reconfigure()
H A Def10_nic.c161 efx_port_t *epp = &(enp->en_port); in ef10_nic_get_port_mode_bandwidth() local
175 if (epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_25000FDX)) in ef10_nic_get_port_mode_bandwidth()
180 if (epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_50000FDX)) in ef10_nic_get_port_mode_bandwidth()
185 if (epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_100000FDX)) in ef10_nic_get_port_mode_bandwidth()
1786 efx_port_t *epp = &(enp->en_port); in ef10_nic_board_cfg() local
1869 if (epp->ep_phy_cap_mask & (1u << EFX_PHY_CAP_BASER_FEC)) in ef10_nic_board_cfg()
1870 epp->ep_phy_cap_mask |= in ef10_nic_board_cfg()
1872 if (epp->ep_phy_cap_mask & (1u << EFX_PHY_CAP_RS_FEC)) in ef10_nic_board_cfg()
1873 epp->ep_phy_cap_mask |= in ef10_nic_board_cfg()
1875 if (epp->ep_phy_cap_mask & (1u << EFX_PHY_CAP_25G_BASER_FEC)) in ef10_nic_board_cfg()
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/freebsd/sys/contrib/device-tree/Bindings/display/tegra/
H A Dnvidia,tegra20-epp.yaml4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-epp.yaml#
15 pattern: "^epp@[0-9a-f]+$"
19 - nvidia,tegra20-epp
20 - nvidia,tegra30-epp
21 - nvidia,tegra114-epp
38 - const: epp
62 epp@540c0000 {
63 compatible = "nvidia,tegra20-epp";
68 reset-names = "epp";
H A Dnvidia,tegra20-host1x.txt149 - epp: encoder pre-processor
152 - compatible: "nvidia,tegra<chip>-epp"
160 - epp
163 - interconnects: Must contain entry for the EPP memory clients.
546 epp {
547 compatible = "nvidia,tegra20-epp";
552 reset-names = "epp";
H A Dnvidia,tegra20-host1x.yaml283 epp@540c0000 {
284 compatible = "nvidia,tegra20-epp";
289 reset-names = "epp";
/freebsd/sys/dev/ppc/
H A Dppc.c99 "COMPATIBLE", "NIBBLE-only", "PS2-only", "PS2/NIBBLE", "EPP-only",
100 "EPP/NIBBLE", "EPP/PS2", "EPP/PS2/NIBBLE", "ECP-only",
101 "ECP/NIBBLE", "ECP/PS2", "ECP/PS2/NIBBLE", "ECP/EPP",
102 "ECP/EPP/NIBBLE", "ECP/EPP/PS2", "ECP/EPP/PS2/NIBBLE", 0
109 "COMPATIBLE", "NIBBLE", "PS/2", "PS/2", "EPP",
110 "EPP", "EPP", "EPP", "ECP",
111 "ECP", "ECP+PS2", "ECP+PS2", "ECP+EPP",
112 "ECP+EPP", "ECP+EPP", "ECP+EPP", 0
115 static char *ppc_epp_protocol[] = { " (EPP 1.9)", " (EPP 1.7)", 0 };
279 * EPP timeout, according to the PC87332 manual
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H A Dppcreg.h102 int ppc_epp; /* EPP mode (1.7 or 1.9) */
131 #define PPC_EPP_ADDR 3 /* EPP address register (8 bit) */
132 #define PPC_EPP_DATA 4 /* EPP data register (8, 16 or 32 bit) */
219 #define SMC_EPPSPP 0x1 /* EPP and SPP */
221 #define SMC_ECPEPP 0x3 /* ECP and EPP */
/freebsd/share/man/man4/
H A Dppc.452 NIBBLE, PS/2, EPP, ECP and other mixed modes.
72 PPB_EPP 0x4 /* EPP mode, 32 bit */
78 bit 4: EPP protocol (0 EPP 1.9, 1 EPP 1.7)
H A Dppbus.4110 Enhanced Parallel Port mode, EPP
112 mixed ECP+EPP or ECP+PS/2 modes
140 Like the EPP protocol, ECP mode provides
154 The EPP protocol was originally developed as a means to provide a high
158 The EPP mode has two types of cycle: address and data.
165 A particularity of the ISA implementation of the EPP protocol is that an
278 native and emulated with ECP and/or EPP.
H A Dhwpstate_intel.476 .It Va dev.hwpstate_intel.%d.epp
82 .It dev.hwpstate_intel.0.epp: 0
/freebsd/contrib/nvi/common/
H A Dsearch.c37 search_init(SCR *sp, dir_t dir, CHAR_T *ptrn, size_t plen, CHAR_T **epp, in search_init() argument
67 if (epp != NULL) in search_init()
68 *epp = ptrn + 1; in search_init()
72 if (epp != NULL) in search_init()
73 *epp = ptrn + 2; in search_init()
116 if (epp != NULL) in search_init()
117 *epp = p; in search_init()
/freebsd/usr.sbin/makefs/msdos/
H A Dmsdosfs_lookup.c200 struct m_buf **bpp, struct direntry **epp) in m_readep() argument
216 if (epp) in m_readep()
217 *epp = bptoep(pmp, *bpp, diroffset); in m_readep()
227 m_readde(struct denode *dep, struct m_buf **bpp, struct direntry **epp) in m_readde() argument
231 bpp, epp)); in m_readde()
/freebsd/sys/dev/ppbus/
H A Dppb_msq.c61 int index, epp, mode; in mode2xfer() local
90 switch ((epp = ppb_get_epp_protocol(bus))) { in mode2xfer()
98 panic("%s: unknown EPP protocol (0x%x)!", __func__, in mode2xfer()
99 epp); in mode2xfer()
H A Dppbconf.h76 #define PPB_EPP 0x4 /* EPP mode, 32 bit */
206 /* EPP standards */
241 * NIBBLE, PS2, EPP or ECP */
H A Dppi.c560 case PPIGEPPD: /* get EPP data bits */ in ppiioctl()
578 case PPISEPPD: /* set EPP data bits */ in ppiioctl()
587 case PPIGEPPA: /* get EPP address bits */ in ppiioctl()
590 case PPISEPPA: /* set EPP address bits */ in ppiioctl()
H A Dppb_base.c93 * Return the chipset EPP protocol
157 * Reset the EPP timeout bit in the status register
/freebsd/usr.sbin/makefs/
H A Dmsdos.h62 int m_readde(struct denode *dep, struct m_buf **bpp, struct direntry **epp);
64 struct m_buf **bpp, struct direntry **epp);
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dzynq-7000.txt1 Device Tree Clock bindings for the Zynq 7000 EPP
3 The Zynq EPP has several different clk providers, each with there own bindings.
/freebsd/sys/geom/
H A Dgeom_event.c386 g_post_event_x(g_event_t *func, void *arg, int flag, int wuflag, struct g_event **epp, va_list ap) in g_post_event_x() argument
397 if (epp != NULL) in g_post_event_x()
398 *epp = ep; in g_post_event_x()

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