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/linux/Documentation/devicetree/bindings/pci/
H A Dnvidia,tegra194-pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Vidya Sagar <vidyas@nvidia.com>
16 inherits all the common properties defined in snps,dw-pcie-ep.yaml. Some
23 Note: On Tegra194's P2972-0000 platform, only C5 controller can be enabled to
29 - nvidia,tegra194-pcie-ep
[all …]
H A Dti-pci.txt4 - compatible: Should be "ti,dra7-pcie" for RC (deprecated)
5 Should be "ti,dra7-pcie-ep" for EP (deprecated)
6 Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode
7 Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode
8 Should be "ti,dra726-pcie-rc" for dra72x in RC mode
9 Should be "ti,dra726-pcie-ep" for dra72x in EP mode
10 - phys : list of PHY specifiers (used by generic PHY framework)
11 - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
13 - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
15 - num-lanes as specified in ../snps,dw-pcie.yaml
[all …]
/linux/arch/powerpc/boot/dts/
H A Dwarp.dts4 * Copyright (c) 2008-2009 PIKA Technologies
12 /dts-v1/;
15 #address-cells = <2>;
16 #size-cells = <1>;
19 dcr-parent = <&{/cpus/cpu@0}>;
27 #address-cells = <1>;
28 #size-cells = <0>;
32 model = "PowerPC,440EP";
34 clock-frequency = <0>; /* Filled in by zImage */
35 timebase-frequency = <0>; /* Filled in by zImage */
[all …]
/linux/arch/arm/boot/dts/qcom/
H A Dqcom-sdx55-telit-fn980-tlb.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
10 #include "qcom-sdx55.dtsi"
15 compatible = "qcom,sdx55-telit-fn980-tlb", "qcom,sdx55";
16 qcom,board-id = <0xb010008 0x0>;
23 stdout-path = "serial0:921600n8";
26 reserved-memory {
27 #address-cells = <1>;
[all …]
H A Dqcom-sdx65-mtp.dts1 // SPDX-License-Identifier: BSD-3-Clause
5 /dts-v1/;
11 #include "qcom-sdx65.dtsi"
12 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
19 compatible = "qcom,sdx65-mtp", "qcom,sdx65";
20 qcom,board-id = <0x2010008 0x302>;
27 stdout-path = "serial0:115200n8";
30 reserved-memory {
31 #address-cells = <1>;
32 #size-cells = <1>;
[all …]
/linux/drivers/staging/media/atomisp/pci/
H A Datomisp_csi2_bridge.c1 // SPDX-License-Identifier: GPL-2.0
8 * Based on drivers/media/pci/intel/ipu3/cio2-bridge.c written by:
18 #include <media/ipu-bridge.h>
19 #include <media/v4l2-fwnode.h>
28 * 79234640-9e10-4fea-a5c1-b5aa8b19756f
52 * 822ace8f-2814-4174-a56b-5f029fe079ee
61 * dc2f6c4f-045b-4f1d-97b9-882a6860a4be
70 * 75c9a639-5c8a-4a00-9f48-a9c3b5da789f
94 * Once all sensors are moved to v4l2-async probing atomisp_gmin_platform.c can
122 DMI_MATCH(DMI_PRODUCT_VERSION, "MIIX 310-10"),
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3399-rock960.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include "rk3399-rock960.dtsi"
14 stdout-path = "serial2:1500000n8";
18 compatible = "gpio-leds";
19 pinctrl-names = "default";
20 pinctrl-0 = <&user_led1_pin>, <&user_led2_pin>,
24 user_led1: led-1 {
26 gpios = <&gpio4 RK_PC2 0>;
27 linux,default-trigger = "heartbeat";
[all …]
H A Drk3399-ficus.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 /dts-v1/;
10 #include "rk3399-rock960.dtsi"
21 stdout-path = "serial2:1500000n8";
24 clkin_gmac: external-gmac-clock {
25 compatible = "fixed-clock";
26 clock-frequency = <125000000>;
27 clock-output-names = "clkin_gmac";
28 #clock-cells = <0>;
32 compatible = "gpio-leds";
[all …]
H A Drk3399-khadas-edge-v.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
8 #include "rk3399-khadas-edge.dtsi"
11 model = "Khadas Edge-V";
12 compatible = "khadas,edge-v", "rockchip,rk3399";
28 ep-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
29 num-lanes = <4>;
H A Drk3399-khadas-edge-captain.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
8 #include "rk3399-khadas-edge.dtsi"
11 model = "Khadas Edge-Captain";
12 compatible = "khadas,edge-captain", "rockchip,rk3399";
28 ep-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
29 num-lanes = <4>;
H A Drk3399-puma-haikou.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include "rk3399-puma.dtsi"
8 #include <dt-bindings/input/input.h>
11 model = "Theobroma Systems RK3399-Q7 SoM";
12 compatible = "tsd,rk3399-puma-haikou", "rockchip,rk3399";
19 stdout-path = "serial0:115200n8";
22 gpio-keys {
23 compatible = "gpio-keys";
24 pinctrl-0 = <&haikou_keys_pin>;
[all …]
H A Drk3399-gru.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2016-2017 Google, Inc
8 #include <dt-bindings/input/input.h>
9 #include "rk3399-op1.dtsi"
18 stdout-path = "serial2:115200n8";
27 * - Rails that only connect to the EC (or devices that the EC talks to)
29 * - Rails _are_ included if the rails go to the AP even if the AP
38 * - The EC controls the enable and the EC always enables a rail as
40 * - The rails are actually connected to each other by a jumper and
45 ppvar_sys: regulator-ppvar-sys {
[all …]
H A Drk3399-gru-scarlet.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Google Gru-scarlet board device tree source
8 #include "rk3399-gru.dtsi"
11 chassis-type = "tablet";
16 pp1250_s3: regulator-pp1250-s3 {
17 compatible = "regulator-fixed";
18 regulator-name = "pp1250_s3";
21 regulator-always-on;
22 regulator-boot-on;
23 regulator-min-microvolt = <1250000>;
[all …]
H A Drk3399-rockpro64.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/input/linux-event-codes.h>
8 #include <dt-bindings/pwm/pwm.h>
20 stdout-path = "serial2:1500000n8";
25 compatible = "pwm-backlight";
26 brightness-levels = <0 4 8 16 32 64 128 255>;
27 default-brightness-level = <5>;
32 clkin_gmac: external-gmac-clock {
33 compatible = "fixed-clock";
34 clock-frequency = <125000000>;
[all …]
H A Drk3399-evb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include <dt-bindings/pwm/pwm.h>
8 #include "rk3399-base.dtsi"
12 compatible = "rockchip,rk3399-evb", "rockchip,rk3399";
20 compatible = "pwm-backlight";
21 brightness-levels = <
54 default-brightness-level = <200>;
58 edp_panel: edp-panel {
59 compatible = "lg,lp079qx1-sp0v";
[all …]
H A Drk3399-kobol-helios64.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
13 /dts-v1/;
26 avdd_0v9_s0: regulator-avdd-0v9-s0 {
27 compatible = "regulator-fixed";
28 regulator-name = "avdd_0v9_s0";
29 regulator-always-on;
30 regulator-boot-on;
31 regulator-min-microvolt = <900000>;
32 regulator-max-microvolt = <900000>;
33 vin-supply = <&vcc1v8_sys_s3>;
[all …]
H A Drk3399-firefly.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include <dt-bindings/input/linux-event-codes.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/pwm/pwm.h>
10 #include <dt-bindings/usb/pd.h>
14 model = "Firefly-RK3399 Board";
15 compatible = "firefly,firefly-rk3399", "rockchip,rk3399";
25 stdout-path = "serial2:1500000n8";
29 compatible = "pwm-backlight";
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8-ss-hsio.dtsi1 // SPDX-License-Identifier: GPL-2.0+
7 #include <dt-bindings/phy/phy.h>
9 hsio_axi_clk: clock-hsio-axi {
10 compatible = "fixed-clock";
11 #clock-cells = <0>;
12 clock-frequency = <400000000>;
13 clock-output-names = "hsio_axi_clk";
16 hsio_per_clk: clock-hsio-per {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
[all …]
H A Dfsl-ls1046a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1046A family SoC.
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/gpio/gpio.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
37 #address-cells = <1>;
[all …]
/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra234-p3768-0000+p3767.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/input/linux-event-codes.h>
4 #include <dt-bindings/input/gpio-keys.h>
6 #include "tegra234-p3767.dtsi"
17 stdout-path = "serial0:115200n8";
22 compatible = "nvidia,tegra194-hsuart";
23 reset-names = "serial";
28 compatible = "nvidia,tegra194-hsuart";
29 reset-names = "serial";
41 vcc-supply = <&vdd_1v8_sys>;
[all …]
/linux/drivers/media/i2c/
H A Dov02a10.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <media/media-entity.h>
14 #include <media/v4l2-async.h>
15 #include <media/v4l2-ctrls.h>
16 #include <media/v4l2-fwnode.h>
17 #include <media/v4l2-subdev.h>
275 struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev); in ov02a10_write_array()
279 for (i = 0; i < r_list->num_of_regs; i++) { in ov02a10_write_array()
280 ret = i2c_smbus_write_byte_data(client, r_list->regs[i].addr, in ov02a10_write_array()
281 r_list->regs[i].val); in ov02a10_write_array()
[all …]
H A Dov4689.c1 // SPDX-License-Identifier: GPL-2.0
16 #include <media/media-entity.h>
17 #include <media/v4l2-async.h>
18 #include <media/v4l2-cci.h>
19 #include <media/v4l2-ctrls.h>
20 #include <media/v4l2-subdev.h>
21 #include <media/v4l2-fwnode.h>
251 /* pre-ISP control */
254 /* OTP-DPC control */
326 fmt->code = MEDIA_BUS_FMT_SBGGR10_1X10; in ov4689_fill_fmt()
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Dmotorola-mapphone-common.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
6 #include "motorola-cpcap-mapphone.dtsi"
10 * We seem to have only 1021 MB accessible, 1021 - 1022 is locked,
11 * then 1023 - 1024 seems to contain mbm.
19 gpio-poweroff {
20 compatible = "gpio-poweroff";
21 pinctrl-0 = <&poweroff_gpio>;
22 pinctrl-names = "default";
[all …]
H A Domap4-sdp.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
5 /dts-v1/;
9 #include "omap4-mcpdm.dtsi"
13 compatible = "ti,omap4-sdp", "ti,omap4430", "ti,omap4";
26 vdd_eth: fixedregulator-vdd-eth {
27 pinctrl-names = "default";
28 pinctrl-0 = <&enet_enable_gpio>;
30 compatible = "regulator-fixed";
31 regulator-name = "VDD_ETH";
[all …]
/linux/drivers/gpio/
H A Dgpiolib-acpi.c1 // SPDX-License-Identifier: GPL-2.0
24 #include "gpiolib-acpi.h"
26 static int run_edge_events_on_boot = -1;
29 "Run edge _AEI event-handlers at boot: 0=no, 1=yes, -1=auto");
50 * struct acpi_gpio_event - ACPI GPIO event handler data
52 * @node: list-entry of the events list of the struct acpi_gpio_chip
95 * struct acpi_gpio_info - ACPI GPIO specific information
132 if (device_match_acpi_handle(&gc->gpiodev->dev, data)) in acpi_gpiochip_find()
136 * When the ACPI device is artificially split to the banks of GPIOs, in acpi_gpiochip_find()
140 * e.g., number of GPIOs in a certain bank. In such case the ACPI handle in acpi_gpiochip_find()
[all …]

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