| /linux/Documentation/devicetree/bindings/cpu/ |
| H A D | idle-states.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cpu/idle-states.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
11 - Anup Patel <anup@brainfault.org>
15 1 - Introduction
18 ARM and RISC-V systems contain HW capable of managing power consumption
19 dynamically, where cores can be put in different low-power states (ranging
22 run-time, can be specified through device tree bindings representing the
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| H A D | cpu-capacity.txt | 6 1 - Introduction
15 2 - CPU capacity definition
19 heterogeneity. Such heterogeneity can come from micro-architectural differences
23 capture a first-order approximation of the relative performance of CPUs.
29 * A "single-threaded" or CPU affine benchmark
43 3 - capacity-dmips-mhz
46 capacity-dmips-mhz is an optional cpu node [1] property: u32 value
51 capacity-dmips-mhz property is all-or-nothing: if it is specified for a cpu
54 available, final capacities are calculated by directly using capacity-dmips-
58 4 - Examples
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| /linux/Documentation/devicetree/bindings/power/ |
| H A D | domain-idle-state.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/power/domain-idle-state.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
18 const: domain-idle-states
21 "^(cpu|cluster|domain)-":
29 const: domain-idle-state
31 entry-latency-us:
33 The worst case latency in microseconds required to enter the idle
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| H A D | power-domain.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/power/power-domain.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rafael J. Wysocki <rjw@rjwysocki.net>
11 - Kevin Hilman <khilman@kernel.org>
12 - Ulf Hansson <ulf.hansson@linaro.org>
25 \#power-domain-cells property in the PM domain provider node.
29 pattern: "^(power-controller|power-domain|performance-domain)([@-].*)?$"
31 domain-idle-states:
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| /linux/kernel/ |
| H A D | latencytop.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * latencytop.c: Latency display infrastructure
10 * CONFIG_LATENCYTOP enables a kernel latency tracking infrastructure that is
11 * used by the "latencytop" userspace tool. The latency that is tracked is not
12 * the 'traditional' interrupt latency (which is primarily caused by something
13 * else consuming CPU), but instead, it is the latency an application encounters
17 * 1) System level latency
18 * 2) Per process latency
20 * The latency is stored in fixed sized data structures in an accumulated form;
21 * if the "same" latency cause is hit twice, this will be tracked as one entry
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| /linux/kernel/trace/ |
| H A D | trace_hwlat.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * trace_hwlat.c - A simple Hardware Latency detector.
20 * Although certain hardware-inducing latencies are necessary (for example,
22 * and remote management) they can wreak havoc upon any OS-level performance
23 * guarantees toward low-latency, especially when the OS is not even made
27 * sampling the built-in CPU timer, looking for discontiguous readings.
31 * environment requiring any kind of low-latency performance
34 * Copyright (C) 2008-2009 Jon Masters, Red Hat, Inc. <jcm@redhat.com>
35 * Copyright (C) 2013-2016 Steven Rostedt, Red Hat, Inc. <srostedt@redhat.com>
67 static char *thread_mode_str[] = { "none", "round-robin", "per-cpu" };
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| /linux/arch/alpha/lib/ |
| H A D | ev6-stxncpy.S | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-stxncpy.S
4 * 21264 version contributed by Rick Gorton <rick.gorton@api-networks.com>
6 * Copy no more than COUNT bytes of the null-terminated string from
29 * Furthermore, v0, a3-a5, t11, and $at are untouched.
34 * ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
36 * E - either cluster
37 * U - upper subcluster; U0 - subcluster U0; U1 - subcluster U1
38 * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
50 doesn't like putting the entry point for a procedure somewhere in the
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| H A D | ev6-stxcpy.S | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-stxcpy.S
4 * 21264 version contributed by Rick Gorton <rick.gorton@alpha-processor.com>
6 * Copy a null-terminated string from SRC to DST.
21 * Furthermore, v0, a3-a5, t11, and t12 are untouched.
26 * ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
28 * E - either cluster
29 * U - upper subcluster; U0 - subcluster U0; U1 - subcluster U1
30 * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
42 doesn't like putting the entry point for a procedure somewhere in the
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| /linux/Documentation/ABI/testing/ |
| H A D | debugfs-intel-iommu | 62 Entry SrcID DstID Vct IRTE_high IRTE_low
68 Entry SrcID DstID Vct IRTE_high IRTE_low
77 Entry SrcID PDA_high PDA_low Vct IRTE_high IRTE_low
87 '-1' and other PASID related fields are invalid.
103 -1 0x0000000000000000:0x0000000000000000:0x0000000000000000
166 * 0 - disable sampling all latency data
168 * 1 - enable sampling IOTLB invalidation latency data
170 * 2 - enable sampling devTLB invalidation latency data
172 * 3 - enable sampling intr entry cache invalidation latency data
181 1) Disable sampling all latency data:
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| /linux/drivers/cpuidle/ |
| H A D | dt_idle_states.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 #define pr_fmt(fmt) "DT idle-states: " fmt
32 idle_state->enter = match_id->data; in init_state_node()
38 idle_state->enter_s2idle = match_id->data; in init_state_node()
40 err = of_property_read_u32(state_node, "wakeup-latency-us", in init_state_node()
41 &idle_state->exit_latency); in init_state_node()
45 err = of_property_read_u32(state_node, "entry-latency-us", in init_state_node()
48 pr_debug(" * %pOF missing entry-latency-us property\n", in init_state_node()
50 return -EINVAL; in init_state_node()
53 err = of_property_read_u32(state_node, "exit-latency-us", in init_state_node()
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| /linux/Documentation/devicetree/bindings/arm/ |
| H A D | psci.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
15 processors") can be used by Linux to initiate various CPU-centric power
25 r0 => 32-bit Function ID / return value
26 {r1 - r3} => Parameters
40 - description:
44 - description:
52 - const: arm,psci-0.2
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| /linux/Documentation/devicetree/bindings/cpufreq/ |
| H A D | nvidia,tegra124-cpufreq.txt | 2 ----------------------------------------------
8 - clocks: Must contain an entry for each entry in clock-names.
9 See ../clocks/clock-bindings.txt for details.
10 - clock-names: Must include the following entries:
11 - cpu_g: Clock mux for the fast CPU cluster.
12 - pll_x: Fast PLL clocksource.
13 - pll_p: Auxiliary PLL used during fast PLL rate changes.
14 - dfll: Fast DFLL clocksource that also automatically scales CPU voltage.
17 - clock-latency: Specify the possible maximum transition latency for clock,
21 --------
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| /linux/kernel/power/ |
| H A D | qos.c | 1 // SPDX-License-Identifier: GPL-2.0-only
15 * or through a built-in notification mechanism.
18 * global CPU latency QoS requests and frequency QoS requests are provided.
50 * pm_qos_read_value - Return the current effective constraint value.
55 return READ_ONCE(c->target_value); in pm_qos_read_value()
60 if (plist_head_empty(&c->list)) in pm_qos_get_value()
61 return c->no_constraint_value; in pm_qos_get_value()
63 switch (c->type) { in pm_qos_get_value()
65 return plist_first(&c->list)->prio; in pm_qos_get_value()
68 return plist_last(&c->list)->prio; in pm_qos_get_value()
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| /linux/block/ |
| H A D | kyber-iosched.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * The Kyber I/O scheduler. Controls latency by throttling queue depths using
18 #include "blk-mq.h"
19 #include "blk-mq-debugfs.h"
20 #include "blk-mq-sched.h"
54 * Maximum device-wide depth for each scheduling domain.
68 * Default latency targets for each scheduling domain.
89 * to the target latency:
91 * <= 1/4 * target latency
92 * <= 1/2 * target latency
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| /linux/arch/arm/mach-sunxi/ |
| H A D | headsmp.S | 1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018 Chen-Yu Tsai
6 * Chen-Yu Tsai <wens@csie.org>
17 ENTRY(sunxi_mc_smp_cluster_cache_enable)
18 .arch armv7-a
20 * Enable cluster-level coherency, in preparation for turning on the MMU.
22 * Also enable regional clock gating and L2 data latency settings for
23 * Cortex-A15. These settings are from the vendor kernel.
34 /* The following is Cortex-A15 specific */
49 /* L2CTRL: L2 data RAM latency */
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| /linux/arch/arm64/boot/dts/sprd/ |
| H A D | ums9620.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <2>;
17 #size-cells = <0>;
19 cpu-map {
50 compatible = "arm,cortex-a55";
52 enable-method = "psci";
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| /linux/drivers/net/ethernet/amazon/ena/ |
| H A D | ena_admin_defs.h | 1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
3 * Copyright 2015-2020 Amazon.com, Inc. or its affiliates. All rights reserved.
13 /* customer metrics - in correlation with
41 /* Additional status is provided in ACQ entry extended_status */
77 /* descriptors and headers are in device memory (a.k.a Low Latency
97 /* completion queue entry for each sq descriptor */
99 /* completion queue entry upon request in sq descriptor */
150 * 1 : ctrl_data - control buffer address valid
151 * 2 : ctrl_data_indirect - control buffer address
173 * 7:5 : sq_direction - 0x1 - Tx; 0x2 - Rx
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| /linux/tools/tracing/latency/ |
| H A D | latency-collector.c | 1 // SPDX-License-Identifier: GPL-2.0
44 C(FUNC_TR, "function-trace"), \
45 C(DISP_GR, "display-graph"), \
134 "No latency tracers are supported by your kernel!\n";
184 struct entry { struct
222 struct entry entries[QUEUE_SIZE];
271 count -= r; in write_or_die()
519 future->tv_se in get_time_in_future()
185 ticketentry global() argument
186 ticket_completed_refentry global() argument
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| /linux/arch/arm64/boot/dts/qcom/ |
| H A D | sm4450.dtsi | 1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sm4450-camcc.h>
8 #include <dt-bindings/clock/qcom,sm4450-dispcc.h>
9 #include <dt-bindings/clock/qcom,sm4450-gcc.h>
10 #include <dt-bindings/clock/qcom,sm4450-gpucc.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
16 interrupt-parent = <&intc>;
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| /linux/Documentation/devicetree/bindings/powerpc/opal/ |
| H A D | power-mgt.txt | 1 IBM Power-Management Bindings
6 node @power-mgt in the device-tree by the firmware.
9 ----------------
12 - name: The name of the idle state as defined by the firmware.
14 - flags: indicating some aspects of this idle states such as the
15 extent of state-loss, whether timebase is stopped on this
18 - exit-latency: The latency involved in transitioning the state of the
21 - target-residency: The minimum time that the CPU needs to reside in
22 this idle state in order to accrue power-savings
26 ----------------
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| /linux/tools/perf/pmu-events/arch/x86/snowridgex/ |
| H A D | uncore-memory.json | 8 …"PublicDescription": "Counts the total number of DRAM Read CAS commands, w/ and w/o auto-pre, issu…
19 … "Counts the total number of DRAM Write CAS commands issued, w/ and w/o auto-pre, on this channel.…
61 …"PublicDescription": "Counts the total number of DRAM Read CAS commands, w/ and w/o auto-pre, issu…
66 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS commands w/auto-pre",
72 …"PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS commands w/auto-pre : DRAM RD…
115 … "Counts the total number of DRAM Write CAS commands issued, w/ and w/o auto-pre, on this channel.…
120 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/o auto-pre",
126 …"PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/o auto-pre : DRAM …
131 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/ auto-pre",
137 …"PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/ auto-pre : DRAM R…
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| /linux/Documentation/arch/arm/omap/ |
| H A D | omap_pm.rst | 6 authors use these functions to communicate minimum latency or
13 - support the range of power management parameters present in the TI SRF;
15 - separate the drivers from the underlying PM parameter
17 latency framework or something else;
19 - specify PM parameters in terms of fundamental units, such as
20 latency and throughput, rather than units which are specific to OMAP
23 - allow drivers which are shared with other architectures (e.g.,
24 DaVinci) to add these constraints in a way which won't affect non-OMAP
27 - can be implemented immediately with minimal disruption of other
34 1. Set the maximum MPU wakeup latency::
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| /linux/arch/arm64/boot/dts/arm/ |
| H A D | juno-r2.dts | 9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/arm/coresight-cti-dt.h>
13 #include "juno-base.dtsi"
14 #include "juno-cs-r1r2.dtsi"
18 compatible = "arm,juno-r2", "arm,juno", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
28 stdout-path = "serial0:115200n8";
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| H A D | juno.dts | 4 * Copyright (c) 2013-2014 ARM Ltd.
9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/arm/coresight-cti-dt.h>
13 #include "juno-base.dtsi"
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
27 stdout-path = "serial0:115200n8";
31 compatible = "arm,psci-0.2";
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| H A D | juno-r1.dts | 9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/arm/coresight-cti-dt.h>
13 #include "juno-base.dtsi"
14 #include "juno-cs-r1r2.dtsi"
18 compatible = "arm,juno-r1", "arm,juno", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
28 stdout-path = "serial0:115200n8";
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