Lines Matching +full:entry +full:- +full:latency
1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018 Chen-Yu Tsai
6 * Chen-Yu Tsai <wens@csie.org>
17 ENTRY(sunxi_mc_smp_cluster_cache_enable)
18 .arch armv7-a
20 * Enable cluster-level coherency, in preparation for turning on the MMU.
22 * Also enable regional clock gating and L2 data latency settings for
23 * Cortex-A15. These settings are from the vendor kernel.
34 /* The following is Cortex-A15 specific */
49 /* L2CTRL: L2 data RAM latency */
55 /* End of Cortex-A15 specific setup */
69 first: .word sunxi_mc_smp_first_comer - .
72 ENTRY(sunxi_mc_smp_secondary_startup)
78 ENTRY(sunxi_mc_smp_resume)