| /linux/drivers/leds/ |
| H A D | leds-lp55xx-common.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
9 * Derived from leds-lp5521.c, leds-lp5523.c
15 #include <linux/led-class-multicolor.h>
53 static LP55XX_DEV_ATTR_RW(engine##nr##_mode, show_engine##nr##_mode, \
69 static LP55XX_DEV_ATTR_RW(engine##nr##_leds, show_engine##nr##_leds, \
79 static LP55XX_DEV_ATTR_WO(engine##nr##_load, store_engine##nr##_load)
116 * @reg_op_mode : Chip specific OP MODE reg addr
117 * @engine_busy : Chip specific engine busy
119 * @reset : Chip specific reset command
120 * @enable : Chip specific enable command
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| /linux/Documentation/leds/ |
| H A D | leds-lp55xx.rst | 8 -----------
14 Device attributes for user-space interface
47 To support device specific configurations, special structure
50 - Maximum number of channels
51 - Reset command, chip enable command
52 - Chip specific initialization
53 - Brightness control register access
54 - Setting LED output current
55 - Program memory address access for running patterns
56 - Additional device specific attributes
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| H A D | leds-lp5562.rst | 15 All four channels can be also controlled using the engine micro programs.
17 For the details, please refer to 'firmware' section in leds-lp55xx.txt
24 Therefore each channel should be mapped to the engine number.
29 Unlike the LP5521/LP5523/55231, LP5562 has unique feature for the engine mux,
35 Red ... Engine 1 (fixed)
36 Green ... Engine 2 (fixed)
37 Blue ... Engine 3 (fixed)
38 White ... Engine 1 or 2 or 3 (selective)
45 the engine selection and loading the firmware.
46 Engine mux has two different mode, RGB and W.
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| /linux/Documentation/driver-api/dmaengine/ |
| H A D | client.rst | 2 DMA Engine API Guide
7 .. note:: For DMA Engine usage in async_tx please see:
8 ``Documentation/crypto/async-tx-api.rst``
11 Below is a guide to device driver writers on how to use the Slave-DMA API of the
12 DMA Engine. This is applicable only for slave DMA usage only.
19 - Allocate a DMA slave channel
21 - Set slave and controller specific parameters
23 - Get a descriptor for transaction
25 - Submit the transaction
27 - Issue pending requests and wait for callback notification
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| /linux/drivers/gpu/drm/sun4i/ |
| H A D | sunxi_engine.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
18 * struct sunxi_engine_ops - helper operations for sunXi engines
27 * This callback allows to prepare our engine for an atomic
34 void (*atomic_begin)(struct sunxi_engine *engine,
40 * This callback allows to validate plane-update related CRTC
41 * constraints specific to engines. This is mirroring the
51 int (*atomic_check)(struct sunxi_engine *engine,
63 void (*commit)(struct sunxi_engine *engine,
71 * the layers supported by that engine.
81 struct sunxi_engine *engine);
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| /linux/Documentation/devicetree/bindings/mtd/ |
| H A D | nand-chip.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/nand-chip.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 - $ref: mtd.yaml#
18 SPI-NAND devices are concerned by this description.
23 Contains the chip-select IDs.
25 nand-ecc-engine:
27 A phandle on the hardware ECC engine if any. There are
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| /linux/Documentation/devicetree/bindings/fsi/ |
| H A D | fsi.txt | 1 FSI bus & engine generic device tree bindings
4 The FSI bus is probe-able, so the OS is able to enumerate FSI slaves, and
6 nodes to probed engines. This allows for fsi engines to expose non-probeable
7 busses, which are then exposed by the device tree. For example, an FSI engine
8 that is an I2C master - the I2C bus can be described by the device tree under
9 the engine's device tree node.
13 the fsi-master-* binding specifications.
18 fsi-master {
19 /* top-level of FSI bus topology, bound to an FSI master driver and
22 fsi-slave@<link,id> {
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| /linux/drivers/gpu/drm/i915/gt/ |
| H A D | intel_engine_pm.c | 1 // SPDX-License-Identifier: MIT
20 static void intel_gsc_idle_msg_enable(struct intel_engine_cs *engine) in intel_gsc_idle_msg_enable() argument
22 struct drm_i915_private *i915 = engine->i915; in intel_gsc_idle_msg_enable()
24 if (MEDIA_VER(i915) >= 13 && engine->id == GSC0) { in intel_gsc_idle_msg_enable()
25 intel_uncore_write(engine->gt->uncore, in intel_gsc_idle_msg_enable()
29 intel_uncore_write(engine->gt->uncore, in intel_gsc_idle_msg_enable()
40 if (ce->state) { in dbg_poison_ce()
41 struct drm_i915_gem_object *obj = ce->state->obj; in dbg_poison_ce()
42 int type = intel_gt_coherent_map_type(ce->engine->gt, obj, true); in dbg_poison_ce()
50 memset(map, CONTEXT_REDZONE, obj->base.size); in dbg_poison_ce()
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| H A D | intel_engine_heartbeat.c | 1 // SPDX-License-Identifier: MIT
17 * While the engine is active, we send a periodic pulse along the engine
18 * to check on its health and to flush any idle-barriers. If that request
19 * is stuck, and we fail to preempt it, we declare the engine hung and
20 * issue a reset -- in the hope that restores progress.
23 static bool next_heartbeat(struct intel_engine_cs *engine) in next_heartbeat() argument
28 delay = READ_ONCE(engine->props.heartbeat_interval_ms); in next_heartbeat()
30 rq = engine->heartbeat.systole; in next_heartbeat()
35 * selftests which override the value and expect specific behaviour. in next_heartbeat()
37 * heartbeat periods (or to override the pre-emption timeout as well, in next_heartbeat()
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| H A D | intel_gt.h | 1 /* SPDX-License-Identifier: MIT */
23 ((gt)->type != GT_MEDIA && \
24 GRAPHICS_VER_FULL((gt)->i915) >= (from) && \
25 GRAPHICS_VER_FULL((gt)->i915) <= (until)))
37 ((gt) && (gt)->type == GT_MEDIA && \
38 MEDIA_VER_FULL((gt)->i915) >= (from) && \
39 MEDIA_VER_FULL((gt)->i915) <= (until)))
42 * Check that the GT is a graphics GT with a specific IP version and has
44 * inclusive, the upper bound is exclusive. The most common use-case of this
59 IS_GRAPHICS_STEP((gt)->i915, (from), (until))))
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| /linux/Documentation/arch/powerpc/ |
| H A D | vas-api.rst | 1 .. SPDX-License-Identifier: GPL-2.0
2 .. _VAS-API:
12 allows both userspace and kernel communicate to co-processor
14 unit comprises of one or more hardware engines or co-processor types
16 userspace applications will have access to only GZIP Compression engine
21 Requests to the GZIP engine must be formatted as a co-processor Request
24 the engine's request queue.
26 The GZIP engine provides two priority levels of requests: Normal and
37 Application access to the GZIP engine is provided through
38 /dev/crypto/nx-gzip device node implemented by the VAS/NX device driver.
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| /linux/drivers/dma/amd/ptdma/ |
| H A D | ptdma.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * -- Based on the CCP driver
25 #include "../../virt-dma.h"
94 #define QUEUE_SIZE_VAL ((ffs(CMD_Q_LEN) - 2) & \
96 #define Q_PTR_MASK (2 << (QUEUE_SIZE_VAL + 5) - 1)
109 #define LSB_COUNT (LSB_END - LSB_START + 1)
124 * struct pt_passthru_engine - pass-through operation
133 * - bit_mod, byte_swap, src, dst, src_len
134 * - mask, mask_len if bit_mod is not PT_PASSTHRU_BITWISE_NOOP
145 * struct pt_cmd - PTDMA operation request
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| /linux/drivers/gpu/drm/amd/display/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: MIT
2 # Copyright © 2019-2024 Advanced Micro Devices, Inc. All rights reserved.
4 menu "Display Engine Configuration"
8 bool "AMD DC - Enable new display engine"
17 Choose this option if you want to use the new display engine
26 https://github.com/llvm/llvm-project/issues/41896.
31 Floating point support, required for DCN-based SoCs
56 This option enables the calculation of crc of specific region via
57 debugfs. Cooperate with specific DMCU FW.
|
| /linux/Documentation/crypto/ |
| H A D | async-tx-api.rst | 1 .. SPDX-License-Identifier: GPL-2.0
32 bulk memory transfers/transforms with support for inter-transactional
34 the details of different hardware offload engine implementations. Code
43 xor-parity-calculations of the md-raid5 driver using the offload engines
51 operation will be offloaded when an engine is available and carried out
54 operations to be submitted, like xor->copy->xor in the raid5 case. The
64 -----------------------------
69 async_<operation>(<op specific parameters>, struct async_submit_ctl *submit)
72 ------------------------
92 -------------------------
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| /linux/drivers/net/ethernet/hisilicon/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
16 for your specific card in the following questions.
36 ports at 10/100 Mbps in full-duplex or half-duplex mode.
71 is needed by any driver which provides HNS acceleration engine or make
72 use of the engine
80 acceleration engine support. The engine is used in Hisilicon hip05,
98 This layer facilitates clients like ENET, RoCE and user-space ethernet
105 tristate "Hisilicon HNS3 HCLGE Acceleration Engine & Compatibility Layer Support"
110 This selects the HNS3_HCLGE network acceleration engine & its hardware
111 compatibility layer. The engine would be used in Hisilicon hip08 family of
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| /linux/drivers/crypto/hisilicon/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
12 Support for Hisilicon SEC Engine in Hip06 and Hip07
35 Support for HiSilicon SEC Engine of version 2 in crypto subsystem.
50 interface. Specific engine driver may use this module.
74 Support for HiSilicon HPRE(High Performance RSA Engine)
|
| /linux/include/uapi/drm/ |
| H A D | ivpu_accel.h | 1 /* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */
3 * Copyright (C) 2020-2025 Intel Corporation
126 * command queue destroy and submit job on specific command queue.
131 * struct drm_ivpu_param - Get/Set VPU parameters
140 * PCI Device ID of the VPU device (read-onl
312 __u32 engine; global() member
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| H A D | i915_drm.h | 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
37 * subject to backwards-compatibility constraints.
43 * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch
46 * track of these events, and if a specific cache-line seems to have a
48 * intel-gpu-tools. The value supplied with the event is always 1.
50 * I915_ERROR_UEVENT - Generated upon error detection, currently only via
57 * I915_RESET_UEVENT - Event is generated just before an attempt to reset the
66 * struct i915_user_extension - Base class for defining a chain of extensions
82 * .. code-block:: C
115 * driver, but rather its scope/meaning is limited to the specific piece
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| /linux/drivers/gpu/drm/arm/ |
| H A D | malidp_regs.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
14 * - DC - display core (general settings)
15 * - DE - display engine
16 * - SE - scaling engine
113 /* Scaling engine registers and masks. */
170 /* register offsets and bits specific to DP500 */
194 #define MALIDP500_LV_YUV2RGB ((s16)(-0xB8))
218 * - RED_ARQOS @ A 4-bit signal value for close to underflow conditions
219 * - GREEN_ARQOS @ A 4-bit signal value for normal conditions
223 /* register offsets and bits specific to DP550/DP650 */
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| /linux/Documentation/driver-api/rapidio/ |
| H A D | mport_cdev.rst | 17 for user-space applications. Most of RapidIO operations are supported through
24 Using available set of ioctl commands user-space applications can perform
27 - Reads and writes from/to configuration registers of mport devices
29 - Reads and writes from/to configuration registers of remote RapidIO devices.
32 - Set RapidIO Destination ID for mport devices (RIO_MPORT_MAINT_HDID_SET)
33 - Set RapidIO Component Tag for mport devices (RIO_MPORT_MAINT_COMPTAG_SET)
34 - Query logical index of mport devices (RIO_MPORT_MAINT_PORT_IDX_GET)
35 - Query capabilities and RapidIO link configuration of mport devices
37 - Enable/Disable reporting of RapidIO doorbell events to user-space applications
39 - Enable/Disable reporting of RIO port-write events to user-space applications
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| /linux/Documentation/devicetree/bindings/gpu/host1x/ |
| H A D | nvidia,tegra210-nvdec.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvdec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Thierry Reding <treding@gmail.com>
16 - Mikko Perttunen <mperttunen@nvidia.com>
20 pattern: "^nvdec@[0-9a-f]*$"
24 - nvidia,tegra210-nvdec
25 - nvidia,tegra186-nvdec
26 - nvidia,tegra194-nvdec
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| H A D | nvidia,tegra210-nvenc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvenc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Thierry Reding <treding@gmail.com>
16 - Mikko Perttunen <mperttunen@nvidia.com>
20 pattern: "^nvenc@[0-9a-f]*$"
24 - nvidia,tegra210-nvenc
25 - nvidia,tegra186-nvenc
26 - nvidia,tegra194-nvenc
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| /linux/drivers/gpu/drm/xe/ |
| H A D | xe_exec_queue_types.h | 1 /* SPDX-License-Identifier: MIT */
25 XE_EXEC_QUEUE_PRIORITY_UNSET = -2, /* For execlist usage only */
35 * struct xe_exec_queue - Execution queue
47 * @hwe: A hardware of the same class. May (physical engine) or may not
48 * (virtual engine) be where jobs actual engine up running. Should never
66 /** @msix_vec: MSI-X vector (for platforms that support it) */
72 * @last_fence: last fence on exec queue, protected by vm->lock in write
73 * mode if bind exec queue, protected by dma resv lock if non-bind exec
80 /* kernel engine only destroyed at driver unload */
84 /* child of VM queue for multi-tile VM jobs */
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| /linux/include/linux/ |
| H A D | hil_mlc.h | 14 * derived from this software without specific prior written permission.
30 * HP-HIL Technical Reference Manual. Hewlett Packard Product No. 45918A
43 /* The HIL has a complicated state engine.
44 * We define the structure of nodes in the state engine here.
70 /* HILSE_IN simply expects any non-errored packet to arrive
104 /* Methods for back-end drivers, e.g. hp_sdc_mlc */
130 void *priv; /* Data specific to a particular type of MLC */
132 int seidx; /* Current node in state engine */
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| /linux/drivers/gpu/drm/i915/ |
| H A D | i915_perf_types.h | 1 /* SPDX-License-Identifier: MIT */
101 * struct i915_perf_stream_ops - the OPs to support a specific stream type
144 * Only write complete records; returning -%ENOSPC if there isn't room
148 * -%ENOSPC or -%EFAULT, even though these may be squashed before
157 * @destroy: Cleanup any stream specific resources.
165 * struct i915_perf_stream - state for a single open stream FD
179 * @engine: Engine associated with this performance stream.
181 struct intel_engine_cs *engine; member
203 * @ctx: %NULL if measuring system-wide across all contexts or a
204 * specific context that is being monitored.
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