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/freebsd/sys/contrib/device-tree/src/arm64/intel/
H A Dkeembay-soc.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-a53";
23 enable-method = "psci";
27 compatible = "arm,cortex-a53";
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/freebsd/contrib/ntp/kernel/sys/
H A Dtimex.h21 * Added defines for hybrid phase/frequency-lock loop.
25 * defines for PPS phase-lock loop.
45 * ntp_gettime - NTP user application interface
56 * ntp_adjtime - NTP daemon application interface
76 * phase-lock loop (PLL) model used in the kernel implementation. These
81 * establishes the timer interrupt frequency, 100 Hz for the SunOS
97 #define SHIFT_KG 6 /* phase factor (shift) */
98 #define SHIFT_KF 16 /* PLL frequency factor (shift) */
99 #define SHIFT_KH 2 /* FLL frequency factor (shift) */
100 #define MAXTC 6 /* maximum time constant (shift) */
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/freebsd/sys/contrib/device-tree/Bindings/regulator/
H A Dmax8973-regulator.txt5 - compatible: must be one of following:
8 - reg: the i2c slave address of the regulator. It should be 0x1b.
15 -maxim,externally-enable: boolean, externally control the regulator output
16 enable/disable.
17 -maxim,enable-gpio: GPIO for enable control. If the valid GPIO is provided
18 then externally enable control will be considered.
19 -maxim,dvs-gpio: GPIO which is connected to DVS pin of device.
20 -maxim,dvs-default-state: Default state of GPIO during initialisation.
22 -maxim,enable-remote-sense: boolean, enable reote sense.
23 -maxim,enable-falling-slew-rate: boolean, enable falling slew rate.
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H A Dmaxim,max8973.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 - $ref: regulator.yaml#
18 - maxim,max8973
19 - maxim,max77621
21 junction-warn-millicelsius:
30 maxim,dvs-gpio:
35 maxim,dvs-default-state:
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/freebsd/lib/libsys/
H A Dntp_adjtime.261 to adjust the phase and frequency of the phase- or frequency-lock loop
78 .Bd -literal
82 long freq; /* frequency offset (scaled ppm) (rw) */
88 long tolerance; /* clock frequency tolerance (scaled
91 * The following read-only structure members are implemented
95 long ppsfreq; /* pps frequency (scaled ppm) (ro) */
97 int shift; /* interval duration (s) (shift) (ro) */
109 .Bl -tag -width tolerance -compact
113 call (write-only).
115 .Bl -tag -width MOD_TIMECONST -compact -offset indent
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/freebsd/sys/contrib/device-tree/src/arm64/amazon/
H A Dalpine-v2.dtsi4 * Antoine Tenart <antoine.tenart@free-electrons.com>
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
35 /dts-v1/;
37 #include <dt-bindings/interrupt-controller/arm-gic.h>
41 compatible = "al,alpine-v2";
42 #address-cells = <2>;
43 #size-cell
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H A Dalpine-v3.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 compatible = "amazon,al-alpine-v3";
14 interrupt-paren
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/freebsd/sys/contrib/device-tree/src/arm64/al/
H A Dalpine-v2.dtsi4 * Antoine Tenart <antoine.tenart@free-electrons.com>
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
35 /dts-v1/;
37 #include <dt-bindings/interrupt-controller/arm-gic.h>
41 compatible = "al,alpine-v2";
42 #address-cells = <2>;
43 #size-cells = <2>;
46 #address-cells = <2>;
47 #size-cells = <0>;
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/freebsd/sys/contrib/device-tree/src/arm64/realtek/
H A Drtd16xx.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <1>;
15 #size-cells = <1>;
17 reserved-memory {
18 #address-cells = <1>;
19 #size-cells = <1>;
32 no-map;
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/freebsd/sys/contrib/device-tree/Bindings/clock/ti/
H A Dapll.txt3 Binding status: Unstable - ABI compatibility may be broken in the future
6 register-mapped APLL with usually two selectable input clocks
13 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
17 - compatible : shall be "ti,dra7-apll-clock" or "ti,omap2-apll-clock"
18 - #clock-cells : from common clock binding; shall be set to 0.
19 - clocks : link phandles of parent clocks (clk-ref and clk-bypass)
20 - reg : address and length of the register set for controlling the APLL.
22 "control" - contains the control register offset
23 "idlest" - contains the idlest register offset
24 "autoidle" - contains the autoidle register offset (OMAP2 only)
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/freebsd/sys/contrib/device-tree/src/arm/rockchip/
H A Drv1126.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rockchip,rv1126-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-binding
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/freebsd/sys/contrib/device-tree/src/arm/broadcom/
H A Dbcm23550.dtsi34 #include <dt-bindings/clock/bcm21664.h>
35 #include <dt-bindings/interrupt-controller/arm-gic.h>
36 #include <dt-bindings/interrupt-controller/irq.h>
39 #address-cells = <1>;
40 #size-cells = <1>;
43 interrupt-parent = <&gic>;
46 #address-cell
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H A Dbcm11351.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2012-2013 Broadcom Corporation
4 #include <dt-bindings/clock/bcm281xx.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-binding
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H A Dbcm21664.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
4 #include <dt-bindings/clock/bcm21664.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/interrupt-controlle
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/freebsd/sys/contrib/device-tree/Bindings/gpio/
H A Dgpio-74x164.txt1 * Generic 8-bits shift register GPIO driver
4 - compatible: Should contain one of the following:
7 - reg : chip select number
8 - gpio-controller : Marks the device node as a gpio controller.
9 - #gpio-cells : Should be two. The first cell is the pin number and
13 - registers-number: Number of daisy-chained shift registers
16 - enable-gpios: GPIO connected to the OE (Output Enable) pin.
23 gpio-controller;
24 #gpio-cells = <2>;
25 registers-number = <4>;
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H A Dfairchild,74hc595.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic 8-bit shift register
10 - Maxime Ripard <mripard@kernel.org>
15 - fairchild,74hc595
16 - nxp,74lvc594
21 gpio-controller: true
23 '#gpio-cells':
28 registers-number:
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H A Dgpio-pisosr.txt1 Generic Parallel-in/Serial-out Shift Register GPIO Driver
3 This binding describes generic parallel-in/serial-out shift register
5 SN74165 serial-out shift registers and the SN65HVS88x series of
9 - compatible : Should be "pisosr-gpio".
10 - gpio-controller : Marks the device node as a GPIO controller.
11 - #gpio-cells : Should be two. For consumer use see gpio.txt.
14 - ngpios : Number of used GPIO lines (0..n-1), default is 8.
15 - load-gpios : GPIO pin specifier attached to load enable, this
20 nodes please refer to ../spi/spi-bus.txt.
25 compatible = "ti,sn65hvs882", "pisosr-gpio";
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/freebsd/sys/sys/
H A Dtimex.h1 /*-
4 * Copyright (c) David L. Mills 1993-2001 *
5 * Copyright (c) Poul-Henning Kamp 2000-2001 *
29 * a joint work between Poul-Henning Kamp and David L. Mills.
44 * kernel discipline loop. Phase or frequency errors greater than
64 #define MOD_FREQUENCY 0x0002 /* set frequency offset */
79 #define STA_PLL 0x0001 /* enable PLL updates (rw) */
80 #define STA_PPSFREQ 0x0002 /* enable PPS freq discipline (rw) */
81 #define STA_PPSTIME 0x0004 /* enable PPS time discipline (rw) */
82 #define STA_FLL 0x0008 /* enable FLL mode (rw) */
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/freebsd/sys/dev/uart/
H A Duart_dev_snps.c1 /*-
117 { "snps,dw-apb-uart", (uintptr_t)&uart_snps_class },
118 { "marvell,armada-38x-uart", (uintptr_t)&uart_snps_class },
149 uint32_t shift, iowidth, clock; in snps_probe() local
159 compat_data)->ocd_data; in snps_probe()
165 sc->ns8250.base.sc_class = uart_class; in snps_probe()
168 if (OF_getencprop(node, "reg-shift", in snps_probe()
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/freebsd/sys/contrib/device-tree/Bindings/serial/
H A D8250.yaml3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - devicetree@vger.kernel.org
13 - $ref: serial.yaml#
14 - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
15 - if:
17 - required:
18 - aspeed,lpc-io-reg
19 - required:
20 - aspeed,lpc-interrupts
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/freebsd/sys/contrib/device-tree/src/arm64/allwinner/
H A Dsun50i-a100.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/sun50i-a100-ccu.h>
8 #include <dt-binding
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/freebsd/sys/contrib/device-tree/src/arm64/broadcom/stingray/
H A Dstingray.dtsi4 * Copyright(c) 2015-2017 Broadcom. All rights reserved.
33 #include <dt-bindings/interrupt-controller/arm-gic.h>
37 interrupt-parent = <&gic>;
38 #address-cells = <2>;
39 #size-cells = <2>;
42 #address-cells = <2>;
43 #size-cells = <0>;
47 compatible = "arm,cortex-a7
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/freebsd/sys/contrib/device-tree/src/arm64/marvell/
H A Dac5-98dx25xx.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cell
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/freebsd/sys/contrib/device-tree/src/arm/amazon/
H A Dalpine.dtsi27 #include <dt-bindings/interrupt-controller/arm-gic.h>
30 #address-cells = <2>;
31 #size-cells = <2>;
42 #address-cells = <1>;
43 #size-cells = <0>;
44 enable-method = "al,alpine-sm
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/freebsd/sys/contrib/device-tree/src/arm/allwinner/
H A Dsun9i-a80.dtsi2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/clock/sun9i-a80-ccu.h>
48 #include <dt-bindings/clock/sun9i-a80-de.h>
49 #include <dt-bindings/clock/sun9i-a80-usb.h>
50 #include <dt-bindings/reset/sun9i-a80-ccu.h>
51 #include <dt-bindings/reset/sun9i-a80-de.h>
52 #include <dt-bindings/reset/sun9i-a80-usb.h>
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