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/linux/Documentation/devicetree/bindings/phy/
H A Dintel,lgm-emmc-phy.yaml4 $id: http://devicetree.org/schemas/phy/intel,lgm-emmc-phy.yaml#
7 title: Intel Lightning Mountain(LGM) eMMC PHY
13 Bindings for eMMC PHY on Intel's Lightning Mountain SoC, syscon
14 node is used to reference the base address of eMMC phy registers.
16 The eMMC PHY node should be the child of a syscon node with the
27 - intel,lgm-emmc-phy
28 - intel,keembay-emmc-phy
59 emmc_phy: emmc-phy@a8 {
60 compatible = "intel,lgm-emmc-phy";
62 clocks = <&emmc>;
[all …]
/linux/Documentation/devicetree/bindings/mmc/
H A Dallwinner,sun4i-a10-mmc.yaml25 - const: allwinner,sun8i-a83t-emmc
28 - const: allwinner,sun50i-a64-emmc
30 - const: allwinner,sun50i-a100-emmc
36 - const: allwinner,sun8i-r40-emmc
37 - const: allwinner,sun50i-a64-emmc
42 - const: allwinner,sun50i-h5-emmc
43 - const: allwinner,sun50i-a64-emmc
48 - const: allwinner,sun50i-h6-emmc
49 - const: allwinner,sun50i-a64-emmc
54 - const: allwinner,sun20i-d1-emmc
[all …]
H A Dmmc-pwrseq-emmc.yaml4 $id: http://devicetree.org/schemas/mmc/mmc-pwrseq-emmc.yaml#
7 title: Simple eMMC hardware reset provider
13 The purpose of this driver is to perform standard eMMC hw reset
16 fix possible issues if bootloader has left eMMC card in initialized or
19 doesn't have hardware reset logic connected to emmc card and (limited or
20 broken) ROM bootloaders are unable to read second stage from the emmc
25 const: mmc-pwrseq-emmc
31 and then deasserted to perform eMMC card reset. To perform
45 compatible = "mmc-pwrseq-emmc";
H A Darasan,sdhci.yaml30 - xlnx,versal-net-emmc
49 - const: rockchip,rk3399-sdhci-5.1 # rk3399 eMMC PHY
66 - const: xlnx,versal-net-emmc # Versal Net eMMC PHY
71 - const: intel,lgm-sdhci-5.1-emmc # Intel LGM eMMC PHY
83 - const: intel,keembay-sdhci-5.1-emmc # Intel Keem Bay eMMC PHY
254 compatible = "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1";
290 compatible = "intel,keembay-sdhci-5.1-emmc", "arasan,sdhci-5.1";
/linux/Documentation/driver-api/mmc/
H A Dmmc-tools.rst16 - Determine the eMMC writeprotect status.
17 - Set the eMMC writeprotect status.
18 - Set the eMMC data sector size to 4KB by disabling emulation.
25 - Enable the eMMC BKOPS feature.
26 - Permanently enable the eMMC H/W Reset feature.
27 - Permanently disable the eMMC H/W Reset feature.
33 - Enable the eMMC cache feature.
34 - Disable the eMMC cache feature.
/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-gxl-s905x-libretech-cc.dts46 emmc_pwrseq: emmc-pwrseq {
47 compatible = "mmc-pwrseq-emmc";
127 /* This is provided by LDOs on the eMMC daugther card */
272 "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3",
273 "eMMC D4", "eMMC D5", "eMMC D6", "eMMC D7",
274 "eMMC Clk", "eMMC Reset", "eMMC CMD",
275 "ALT BOOT MODE", "", "", "", "eMMC Data Strobe",
323 /* eMMC */
H A Dmeson-gxl-s905x-khadas-vim.dts184 "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3",
185 "eMMC D4", "eMMC D5", "eMMC D6", "eMMC D7",
186 "eMMC Clk", "eMMC Reset", "eMMC CMD",
187 "", "BOOT_MODE", "", "", "eMMC Data Strobe",
H A Dmeson-gxl-s805x-libretech-ac.dts53 emmc_pwrseq: emmc-pwrseq {
54 compatible = "mmc-pwrseq-emmc";
249 "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3",
250 "eMMC D4", "eMMC D5", "eMMC D6", "eMMC D7",
251 "eMMC Clk", "eMMC Reset", "eMMC CMD",
280 /* eMMC */
H A Dmeson-gxbb-odroidc2.dts161 emmc_pwrseq: emmc-pwrseq {
162 compatible = "mmc-pwrseq-emmc";
302 "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3", "eMMC D4",
303 "eMMC D5", "eMMC D6", "eMMC D7", "eMMC Clk",
304 "eMMC Reset", "eMMC CMD",
364 /* eMMC */
H A Dmeson-gxbb-nanopi-k2.dts107 emmc_pwrseq: emmc-pwrseq {
108 compatible = "mmc-pwrseq-emmc";
260 "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3", "eMMC D4",
261 "eMMC D5", "eMMC D6", "eMMC D7", "eMMC Clk",
262 "eMMC Reset", "eMMC CMD",
263 "", "", "", "", "eMMC DS",
362 /* eMMC */
/linux/arch/arm/boot/dts/amlogic/
H A Dmeson8b-ec100.dts30 emmc_pwrseq: emmc-pwrseq {
31 compatible = "mmc-pwrseq-emmc";
427 "NAND_D0 (EMMC)", "NAND_D1 (EMMC)",
428 "NAND_D2 (EMMC)", "NAND_D3 (EMMC)",
429 "NAND_D4 (EMMC)", "NAND_D5 (EMMC)",
430 "NAND_D6 (EMMC)", "NAND_D7 (EMMC)",
431 "NAND_CS1 (EMMC)", "NAND_CS2 iNAND_RS1 (EMMC)",
432 "NAND_nR/B iNAND_CMD (EMMC)", "NAND_ALE (EMMC)",
433 "NAND_CLE (EMMC)", "nRE_S1 NAND_nRE (EMMC)",
434 "nWE_S1 NAND_nWE (EMMC)", "", "", "", "SPI_CS",
/linux/arch/arm/boot/dts/allwinner/
H A Dsun7i-a20-olimex-som-evb-emmc.dts3 * Device Tree Source for A20-Olimex-SOM-EVB-eMMC Board
14 model = "Olimex A20-Olimex-SOM-EVB-eMMC";
15 compatible = "olimex,a20-olimex-som-evb-emmc", "allwinner,sun7i-a20";
18 compatible = "mmc-pwrseq-emmc";
30 emmc: emmc@0 { label
H A Dsun7i-a20-olimex-som204-evb-emmc.dts3 * Device Tree Source for A20-SOM204-EVB-eMMC Board
13 model = "Olimex A20-SOM204-EVB-eMMC";
14 compatible = "olimex,a20-olimex-som204-evb-emmc", "allwinner,sun7i-a20";
17 compatible = "mmc-pwrseq-emmc";
29 emmc: emmc@0 { label
H A Dsun7i-a20-olinuxino-lime-emmc.dts10 model = "Olimex A20-OLinuXino-LIME-eMMC";
11 compatible = "olimex,a20-olinuxino-lime-emmc", "allwinner,sun7i-a20";
14 compatible = "mmc-pwrseq-emmc";
27 emmc: emmc@0 { label
H A Dsun7i-a20-olinuxino-micro-emmc.dts47 model = "Olimex A20-OLinuXino-MICRO-eMMC";
48 compatible = "olimex,a20-olinuxino-micro-emmc", "allwinner,sun7i-a20";
51 compatible = "mmc-pwrseq-emmc";
63 emmc: emmc@0 { label
H A Dsun7i-a20-olinuxino-lime2-emmc.dts47 model = "Olimex A20-OLinuXino-LIME2-eMMC";
48 compatible = "olimex,a20-olinuxino-lime2-emmc", "allwinner,sun7i-a20";
51 compatible = "mmc-pwrseq-emmc";
64 emmc: emmc@0 { label
/linux/Documentation/devicetree/bindings/soc/intel/
H A Dintel,lgm-syscon.yaml31 "^emmc-phy@[0-9a-f]+$":
32 $ref: /schemas/phy/intel,lgm-emmc-phy.yaml#
51 emmc-phy@a8 {
52 compatible = "intel,lgm-emmc-phy";
54 clocks = <&emmc>;
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6ull-colibri-emmc-iris.dts8 #include "imx6ull-colibri-emmc-nonwifi.dtsi"
12 model = "Toradex Colibri iMX6ULL 1GB (eMMC) on Colibri Iris";
13 compatible = "toradex,colibri-imx6ull-emmc-iris",
14 "toradex,colibri-imx6ull-emmc",
H A Dimx6ull-colibri-emmc-eval-v3.dts8 #include "imx6ull-colibri-emmc-nonwifi.dtsi"
12 model = "Toradex Colibri iMX6ULL 1GB (eMMC) on Colibri Evaluation Board V3";
13 compatible = "toradex,colibri-imx6ull-emmc-eval",
14 "toradex,colibri-imx6ull-emmc",
H A Dimx6ull-colibri-emmc-aster.dts8 #include "imx6ull-colibri-emmc-nonwifi.dtsi"
12 model = "Toradex Colibri iMX6ULL 1GB (eMMC) on Colibri Aster";
13 compatible = "toradex,colibri-imx6ull-emmc-aster",
14 "toradex,colibri-imx6ull-emmc",
H A Dimx6ull-colibri-emmc-iris-v2.dts8 #include "imx6ull-colibri-emmc-nonwifi.dtsi"
12 model = "Toradex Colibri iMX6ULL 1G (eMMC) on Colibri Iris V2";
13 compatible = "toradex,colibri-imx6ull-emmc-iris-v2",
14 "toradex,colibri-imx6ull-emmc",
H A Dimx7d-colibri-emmc-aster.dts8 #include "imx7d-colibri-emmc.dtsi"
12 model = "Toradex Colibri iMX7D 1GB (eMMC) on Aster Carrier Board";
13 compatible = "toradex,colibri-imx7d-emmc-aster",
14 "toradex,colibri-imx7d-emmc",
H A Dimx7d-colibri-emmc-eval-v3.dts7 #include "imx7d-colibri-emmc.dtsi"
11 model = "Toradex Colibri iMX7D 1GB (eMMC) on Colibri Evaluation Board V3";
12 compatible = "toradex,colibri-imx7d-emmc-eval-v3",
13 "toradex,colibri-imx7d-emmc",
/linux/drivers/mmc/host/
H A Dsdhci-xenon-phy.c20 /* Register base for eMMC PHY 5.0 Version */
22 /* Register base for eMMC PHY 5.1 Version */
117 * in eMMC PHY 5.0 or eMMC PHY 5.1
139 "emmc 5.0 phy",
140 "emmc 5.1 phy"
187 * eMMC PHY configuration and operations
236 * eMMC 5.0/5.1 PHY init/re-init.
237 * eMMC PHY init should be executed after:
300 dev_err(mmc_dev(host->mmc), "eMMC PHY init cannot complete after %d us\n", in xenon_emmc_phy_init()
346 * Enable eMMC PHY HW DLL
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/linux/drivers/phy/intel/
H A DKconfig6 tristate "Intel Keem Bay EMMC PHY driver"
15 will be called phy-keembay-emmc.ko.
44 tristate "Intel Lightning Mountain EMMC PHY driver"
48 Enable this to support the Intel EMMC PHY

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