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/linux/Documentation/devicetree/bindings/phy/
H A Dintel,lgm-emmc-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/intel,lgm-emmc-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Intel Lightning Mountain(LGM) eMMC PHY
10 - Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
13 Bindings for eMMC PHY on Intel's Lightning Mountain SoC, syscon
14 node is used to reference the base address of eMMC phy registers.
16 The eMMC PHY node should be the child of a syscon node with the
19 - compatible: Should be one of the following:
[all …]
H A Drockchip,rk3399-emmc-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip,rk3399-emmc-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip EMMC PHY
10 - Heiko Stuebner <heiko@sntech.de>
14 const: rockchip,rk3399-emmc-phy
22 clock-names:
25 drive-impedance-ohm:
32 rockchip,enable-strobe-pulldown:
[all …]
/linux/Documentation/devicetree/bindings/mmc/
H A Dmarvell,xenon-sdhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/marvell,xenon-sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 mmc-controller.yaml and the properties used by the Xenon implementation.
15 sets, clock and PHY.
20 - Ulf Hansson <ulf.hansson@linaro.org>
25 - enum:
26 - marvell,armada-cp110-sdhci
27 - marvell,armada-ap806-sdhci
[all …]
H A Darasan,sdhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Adrian Hunter <adrian.hunter@intel.com>
13 - $ref: mmc-controller.yaml#
14 - if:
18 const: arasan,sdhci-5.1
21 - phys
22 - phy-names
23 - if:
[all …]
H A Dcdns,sdhci.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence SD/SDIO/eMMC Host Controller (SD4HC)
10 - Masahiro Yamada <yamada.masahiro@socionext.com>
15 - enum:
16 - amd,pensando-elba-sd4hc
17 - microchip,mpfs-sd4hc
18 - microchip,pic64gx-sd4hc
19 - mobileye,eyeq-sd4hc
[all …]
/linux/drivers/mmc/host/
H A Dsdhci-xenon-phy.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * PHY support for Xenon SDHC
8 * Date: 2016-8-24
17 #include "sdhci-pltfm.h"
18 #include "sdhci-xenon.h"
20 /* Register base for eMMC PHY 5.0 Version */
22 /* Register base for eMMC PHY 5.1 Version */
116 * List offset of PHY registers and some special register values
117 * in eMMC PHY 5.0 or eMMC PHY 5.1
139 "emmc 5.0 phy",
[all …]
/linux/drivers/phy/intel/
H A Dphy-intel-lgm-emmc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Intel eMMC PHY driver
14 #include <linux/phy/phy.h>
18 /* eMMC phy register definitions */
51 static int intel_emmc_phy_power(struct phy *phy, bool on_off) in intel_emmc_phy_power() argument
53 struct intel_emmc_phy *priv = phy_get_drvdata(phy); in intel_emmc_phy_power()
64 ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL1_REG, PDB_MASK, in intel_emmc_phy_power()
67 dev_err(&phy->dev, "CALIO power down bar failed: %d\n", ret); in intel_emmc_phy_power()
75 rate = clk_get_rate(priv->emmcclk); in intel_emmc_phy_power()
78 dev_warn(&phy->dev, "Unsupported rate: %lu\n", rate); in intel_emmc_phy_power()
[all …]
H A Dphy-intel-keembay-emmc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Intel Keem Bay eMMC PHY driver
14 #include <linux/phy/phy.h>
18 /* eMMC/SD/SDIO core/phy configuration registers */
53 static int keembay_emmc_phy_power(struct phy *phy, bool on_off) in keembay_emmc_phy_power() argument
55 struct keembay_emmc_phy *priv = phy_get_drvdata(phy); in keembay_emmc_phy_power()
66 ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, PWR_DOWN_MASK, in keembay_emmc_phy_power()
69 dev_err(&phy->dev, "CALIO power down bar failed: %d\n", ret); in keembay_emmc_phy_power()
73 ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, DLL_EN_MASK, in keembay_emmc_phy_power()
76 dev_err(&phy->dev, "turn off the dll failed: %d\n", ret); in keembay_emmc_phy_power()
[all …]
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
3 # Phy drivers for Intel platforms
6 tristate "Intel Keem Bay EMMC PHY driver"
15 will be called phy-keembay-emmc.ko.
18 tristate "Intel Keem Bay USB PHY driver"
27 will be called phy-keembay-usb.ko.
44 tristate "Intel Lightning Mountain EMMC PHY driver"
48 Enable this to support the Intel EMMC PHY
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_PHY_INTEL_KEEMBAY_EMMC) += phy-intel-keembay-emmc.o
3 obj-$(CONFIG_PHY_INTEL_KEEMBAY_USB) += phy-intel-keembay-usb.o
4 obj-$(CONFIG_PHY_INTEL_LGM_COMBO) += phy-intel-lgm-combo.o
5 obj-$(CONFIG_PHY_INTEL_LGM_EMMC) += phy-intel-lgm-emmc.o
/linux/Documentation/devicetree/bindings/soc/intel/
H A Dintel,lgm-syscon.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/soc/intel/intel,lgm-syscon.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chuanhua Lei <lchuanhua@maxlinear.com>
11 - Rahul Tanwar <rtanwar@maxlinear.com>
16 - const: intel,lgm-syscon
17 - const: syscon
24 "#address-cells":
27 "#size-cells":
[all …]
/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-gxbb-nanopi-k2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "meson-gxbb.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/sound/meson-aiu.h>
13 compatible = "friendlyarm,nanopi-k2", "amlogic,meson-gxbb";
22 stdout-path = "serial0:115200n8";
31 compatible = "gpio-leds";
33 led-stat {
34 label = "nanopi-k2:blue:stat";
[all …]
H A Dmeson-gxm-nexbox-a1.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
10 /dts-v1/;
12 #include "meson-gxm.dtsi"
13 #include <dt-bindings/sound/meson-aiu.h>
16 compatible = "nexbox,a1", "amlogic,s912", "amlogic,meson-gxm";
25 stdout-path = "serial0:115200n8";
28 spdif_dit: audio-codec-0 {
29 #sound-dai-cells = <0>;
30 compatible = "linux,spdif-dit";
31 sound-name-prefix = "DIT";
[all …]
/linux/arch/arm64/boot/dts/renesas/
H A Drzg2l-smarc-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irqc-rzg2l.h>
10 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
12 /* SW1[2] should be at position 2/OFF to enable 64 GB eMMC */
13 #define EMMC 1 macro
18 * Disable eMMC by setting "#define EMMC 0" above.
20 #define SDHI (!EMMC)
38 reg_1p8v: regulator-1p8v {
39 compatible = "regulator-fixed";
[all …]
/linux/drivers/pinctrl/berlin/
H A Dpinctrl-as370.c1 // SPDX-License-Identifier: GPL-2.0
22 BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG0 */
26 BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG1 */
31 BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG2 */
36 BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG3 */
42 BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG4 */
49 BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG5 */
53 BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG6 */
57 BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG7 */
61 BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG8 */
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Dpx30-ringneck.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/leds/common.h>
13 mmc0 = &emmc;
20 attiny-updi-gate-regulator {
21 compatible = "regulator-output";
22 vout-supply = <&vg_attiny_updi>;
25 emmc_pwrseq: emmc-pwrseq {
26 compatible = "mmc-pwrseq-emmc";
27 pinctrl-0 = <&emmc_reset>;
[all …]
H A Drk3328-nanopi-r2s-plus.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 /dts-v1/;
11 #include "rk3328-nanopi-r2s.dtsi"
14 compatible = "friendlyarm,nanopi-r2s-plus", "rockchip,rk3328";
18 mmc1 = &emmc;
22 &emmc {
23 bus-width = <8>;
24 cap-mmc-highspeed;
25 disable-wp;
26 mmc-hs200-1_8v;
[all …]
H A Dpx30-cobra.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/leds/common.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
16 mmc0 = &emmc;
20 stdout-path = "serial5:115200n8";
24 compatible = "pwm-backlight";
25 power-supply = <&vcc5v0_sys>;
[all …]
/linux/arch/riscv/boot/dts/sophgo/
H A Dsg2042-evb-v2.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
13 compatible = "sophgo,sg2042-evb-v2", "sophgo,sg2042";
16 stdout-path = "serial0";
19 pwmfan: pwm-fan {
20 compatible = "pwm-fan";
21 cooling-levels = <103 128 179 230 255>;
23 #cooling-cells = <2>;
26 thermal-zones {
[all …]
H A Dsg2042-evb-v1.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
13 compatible = "sophgo,sg2042-evb-v1", "sophgo,sg2042";
16 stdout-path = "serial0";
19 gpio-power {
20 compatible = "gpio-keys";
22 key-power {
26 linux,input-type = <EV_KEY>;
27 debounce-interval = <100>;
[all …]
/linux/arch/arm/boot/dts/amlogic/
H A Dmeson8b-odroidc1.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
12 model = "Hardkernel ODROID-C1";
13 compatible = "hardkernel,odroid-c1", "amlogic,meson8b";
22 stdout-path = "serial0:115200n8";
30 emmc_pwrseq: emmc-pwrseq {
31 compatible = "mmc-pwrseq-emmc";
32 reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
36 compatible = "gpio-leds";
[all …]
H A Dmeson8b-ec100.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
22 stdout-path = "serial0:115200n8";
30 emmc_pwrseq: emmc-pwrseq {
31 compatible = "mmc-pwrseq-emmc";
32 reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
35 gpio-keys {
36 compatible = "gpio-keys-polled";
[all …]
/linux/drivers/phy/rockchip/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Rockchip platforms
6 tristate "Rockchip Display Port PHY Driver"
10 Enable this to support the Rockchip Display Port PHY.
22 will be called phy-rockchip-dphy-rx0.
25 tristate "Rockchip EMMC PHY Driver"
29 Enable this to support the Rockchip EMMC PHY.
32 tristate "Rockchip INNO HDMI PHY Driver"
38 Enable this to support the Rockchip Innosilicon HDMI PHY.
49 Support for Rockchip USB2.0 PHY with Innosilicon IP block.
[all …]
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt7622-rfb1.dts6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 /dts-v1/;
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/gpio/gpio.h>
18 chassis-type = "embedded";
19 compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
26 stdout-path = "serial0:115200n8";
32 proc-supply = <&mt6380_vcpu_reg>;
33 sram-supply = <&mt6380_vm_reg>;
37 proc-supply = <&mt6380_vcpu_reg>;
[all …]
H A Dmt7622-bananapi-bpi-r64.dts5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 /dts-v1/;
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/leds/common.h>
17 model = "Bananapi BPI-R64";
18 chassis-type = "embedded";
19 compatible = "bananapi,bpi-r64", "mediatek,mt7622";
26 stdout-path = "serial0:115200n8";
32 proc-supply = <&mt6380_vcpu_reg>;
[all …]

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