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/linux/drivers/memory/tegra/
H A Dtegra210-emc-table.c1 // SPDX-License-Identifier: GPL-2.0
8 #include "tegra210-emc.h"
15 struct tegra210_emc *emc = dev_get_drvdata(dev); in tegra210_emc_table_device_init() local
16 struct tegra210_emc_timing *timings; in tegra210_emc_table_device_init() local
19 timings = memremap(rmem->base, rmem->size, MEMREMAP_WB); in tegra210_emc_table_device_init()
20 if (!timings) { in tegra210_emc_table_device_init()
21 dev_err(dev, "failed to map EMC table\n"); in tegra210_emc_table_device_init()
22 return -ENOMEM; in tegra210_emc_table_device_init()
26 if (timings[i].revision == 0) in tegra210_emc_table_device_init()
33 if (emc->derated) { in tegra210_emc_table_device_init()
[all …]
H A Dtegra20-emc.c1 // SPDX-License-Identifier: GPL-2.0
14 #include <linux/interconnect-provider.h>
206 struct emc_timing *timings; member
216 * There are multiple sources in the EMC driver which could request
221 /* protect shared rate-change code path */
237 struct tegra_emc *emc = data; in tegra_emc_isr() local
241 status = readl_relaxed(emc->reg in tegra_emc_isr()
256 tegra_emc_find_timing(struct tegra_emc * emc,unsigned long rate) tegra_emc_find_timing() argument
277 emc_prepare_timing_change(struct tegra_emc * emc,unsigned long rate) emc_prepare_timing_change() argument
299 emc_complete_timing_change(struct tegra_emc * emc,bool flush) emc_complete_timing_change() argument
327 struct tegra_emc *emc = container_of(nb, struct tegra_emc, clk_nb); tegra_emc_clk_change_notify() local
355 load_one_timing_from_dt(struct tegra_emc * emc,struct emc_timing * timing,struct device_node * node) load_one_timing_from_dt() argument
410 tegra_emc_load_timings_from_dt(struct tegra_emc * emc,struct device_node * node) tegra_emc_load_timings_from_dt() argument
458 tegra_emc_find_node_by_ram_code(struct tegra_emc * emc) tegra_emc_find_node_by_ram_code() argument
538 emc_read_lpddr_mode_register(struct tegra_emc * emc,unsigned int emem_dev,unsigned int register_addr,unsigned int * register_data) emc_read_lpddr_mode_register() argument
574 emc_read_lpddr_sdram_info(struct tegra_emc * emc,unsigned int emem_dev,bool print_out) emc_read_lpddr_sdram_info() argument
596 emc_setup_hw(struct tegra_emc * emc) emc_setup_hw() argument
681 struct tegra_emc *emc = arg; emc_round_rate() local
716 tegra_emc_rate_requests_init(struct tegra_emc * emc) tegra_emc_rate_requests_init() argument
726 emc_request_rate(struct tegra_emc * emc,unsigned long new_min_rate,unsigned long new_max_rate,enum emc_rate_request_type type) emc_request_rate() argument
767 emc_set_min_rate(struct tegra_emc * emc,unsigned long rate,enum emc_rate_request_type type) emc_set_min_rate() argument
780 emc_set_max_rate(struct tegra_emc * emc,unsigned long rate,enum emc_rate_request_type type) emc_set_max_rate() argument
818 tegra_emc_validate_rate(struct tegra_emc * emc,unsigned long rate) tegra_emc_validate_rate() argument
831 struct tegra_emc *emc = s->private; tegra_emc_debug_available_rates_show() local
848 struct tegra_emc *emc = data; tegra_emc_debug_min_rate_get() local
857 struct tegra_emc *emc = data; tegra_emc_debug_min_rate_set() local
878 struct tegra_emc *emc = data; tegra_emc_debug_max_rate_get() local
887 struct tegra_emc *emc = data; tegra_emc_debug_max_rate_set() local
906 tegra_emc_debugfs_init(struct tegra_emc * emc) tegra_emc_debugfs_init() argument
983 struct tegra_emc *emc = to_tegra_emc_provider(dst->provider); emc_icc_set() local
1006 tegra_emc_interconnect_init(struct tegra_emc * emc) tegra_emc_interconnect_init() argument
1072 struct tegra_emc *emc = data; devm_tegra_emc_unreg_clk_notifier() local
1077 tegra_emc_init_clk(struct tegra_emc * emc) tegra_emc_init_clk() argument
1111 struct tegra_emc *emc = dev_get_drvdata(dev); tegra_emc_devfreq_target() local
1130 struct tegra_emc *emc = dev_get_drvdata(dev); tegra_emc_devfreq_get_dev_status() local
1156 tegra_emc_devfreq_init(struct tegra_emc * emc) tegra_emc_devfreq_init() argument
1193 struct tegra_emc *emc; tegra_emc_probe() local
[all...]
H A Dtegra30-emc.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Based on downstream driver from NVIDIA and tegra124-emc.c
6 * Copyright (C) 2011-2014 NVIDIA Corporation
9 * Copyright (C) 2019 GRATE-DRIVER project
18 #include <linux/interconnect-provider.h>
366 struct emc_timing *timings; member
387 * There are multiple sources in the EMC drive
398 emc_seq_update_timing(struct tegra_emc * emc) emc_seq_update_timing() argument
418 struct tegra_emc *emc = data; tegra_emc_isr() local
437 emc_find_timing(struct tegra_emc * emc,unsigned long rate) emc_find_timing() argument
458 emc_dqs_preset(struct tegra_emc * emc,struct emc_timing * timing,bool * schmitt_to_vref) emc_dqs_preset() argument
501 emc_prepare_mc_clk_cfg(struct tegra_emc * emc,unsigned long rate) emc_prepare_mc_clk_cfg() argument
523 emc_prepare_timing_change(struct tegra_emc * emc,unsigned long rate) emc_prepare_timing_change() argument
792 emc_complete_timing_change(struct tegra_emc * emc,unsigned long rate) emc_complete_timing_change() argument
843 emc_unprepare_timing_change(struct tegra_emc * emc,unsigned long rate) emc_unprepare_timing_change() argument
858 struct tegra_emc *emc = container_of(nb, struct tegra_emc, clk_nb); emc_clk_change_notify() local
888 load_one_timing_from_dt(struct tegra_emc * emc,struct emc_timing * timing,struct device_node * node) load_one_timing_from_dt() argument
956 emc_check_mc_timings(struct tegra_emc * emc) emc_check_mc_timings() argument
979 emc_load_timings_from_dt(struct tegra_emc * emc,struct device_node * node) emc_load_timings_from_dt() argument
1026 emc_find_node_by_ram_code(struct tegra_emc * emc) emc_find_node_by_ram_code() argument
1059 emc_read_lpddr_mode_register(struct tegra_emc * emc,unsigned int emem_dev,unsigned int register_addr,unsigned int * register_data) emc_read_lpddr_mode_register() argument
1095 emc_read_lpddr_sdram_info(struct tegra_emc * emc,unsigned int emem_dev) emc_read_lpddr_sdram_info() argument
1118 emc_setup_hw(struct tegra_emc * emc) emc_setup_hw() argument
1199 struct tegra_emc *emc = arg; emc_round_rate() local
1234 tegra_emc_rate_requests_init(struct tegra_emc * emc) tegra_emc_rate_requests_init() argument
1244 emc_request_rate(struct tegra_emc * emc,unsigned long new_min_rate,unsigned long new_max_rate,enum emc_rate_request_type type) emc_request_rate() argument
1285 emc_set_min_rate(struct tegra_emc * emc,unsigned long rate,enum emc_rate_request_type type) emc_set_min_rate() argument
1298 emc_set_max_rate(struct tegra_emc * emc,unsigned long rate,enum emc_rate_request_type type) emc_set_max_rate() argument
1336 tegra_emc_validate_rate(struct tegra_emc * emc,unsigned long rate) tegra_emc_validate_rate() argument
1349 struct tegra_emc *emc = s->private; tegra_emc_debug_available_rates_show() local
1366 struct tegra_emc *emc = data; tegra_emc_debug_min_rate_get() local
1375 struct tegra_emc *emc = data; tegra_emc_debug_min_rate_set() local
1396 struct tegra_emc *emc = data; tegra_emc_debug_max_rate_get() local
1405 struct tegra_emc *emc = data; tegra_emc_debug_max_rate_set() local
1424 tegra_emc_debugfs_init(struct tegra_emc * emc) tegra_emc_debugfs_init() argument
1501 struct tegra_emc *emc = to_tegra_emc_provider(dst->provider); emc_icc_set() local
1524 tegra_emc_interconnect_init(struct tegra_emc * emc) tegra_emc_interconnect_init() argument
1584 struct tegra_emc *emc = data; devm_tegra_emc_unreg_clk_notifier() local
1589 tegra_emc_init_clk(struct tegra_emc * emc) tegra_emc_init_clk() argument
1624 struct tegra_emc *emc; tegra_emc_probe() local
1695 struct tegra_emc *emc = dev_get_drvdata(dev); tegra_emc_suspend() local
1716 struct tegra_emc *emc = dev_get_drvdata(dev); tegra_emc_resume() local
[all...]
H A Dtegra210-emc-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.
21 #include "tegra210-emc.h"
22 #include "tegra210-mc.h"
62 next->trim_regs[EMC_PMACRO_OB_DDLL_LONG_DQ_RANK ## \
69 next->trim_perch_regs[EMC ## chan ## \
561 struct tegra210_emc *emc = from_timer(emc, timer, training); in tegra210_emc_train() local
564 if (!emc->last) in tegra210_emc_train()
567 spin_lock_irqsave(&emc->lock, flags); in tegra210_emc_train()
569 if (emc->sequence->periodic_compensation) in tegra210_emc_train()
[all …]
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
21 This driver is for the External Memory Controller (EMC) found on
22 Tegra20 chips. The EMC controls the external DRAM on the board.
23 This driver is required to change memory timings / clock rate for
33 This driver is for the External Memory Controller (EMC) found on
34 Tegra30 chips. The EMC controls the external DRAM on the board.
35 This driver is required to change memory timings / clock rate for
45 This driver is for the External Memory Controller (EMC) found on
46 Tegra124 chips. The EMC controls the external DRAM on the board.
47 This driver is required to change memory timings / clock rate for
[all …]
H A Dtegra124-emc.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
15 #include <linux/interconnect-provider.h>
495 struct emc_timing *timings; member
507 * There are multiple sources in the EMC driver which could request
512 /* protect shared rate-change code path */
518 static void emc_ccfifo_writel(struct tegra_emc *emc, u3 argument
525 emc_seq_update_timing(struct tegra_emc * emc) emc_seq_update_timing() argument
542 emc_seq_disable_auto_cal(struct tegra_emc * emc) emc_seq_disable_auto_cal() argument
559 emc_seq_wait_clkchange(struct tegra_emc * emc) emc_seq_wait_clkchange() argument
574 tegra_emc_find_timing(struct tegra_emc * emc,unsigned long rate) tegra_emc_find_timing() argument
595 tegra_emc_prepare_timing_change(struct tegra_emc * emc,unsigned long rate) tegra_emc_prepare_timing_change() argument
823 tegra_emc_complete_timing_change(struct tegra_emc * emc,unsigned long rate) tegra_emc_complete_timing_change() argument
880 emc_read_current_timing(struct tegra_emc * emc,struct emc_timing * timing) emc_read_current_timing() argument
899 emc_init(struct tegra_emc * emc) emc_init() argument
920 load_one_timing_from_dt(struct tegra_emc * emc,struct emc_timing * timing,struct device_node * node) load_one_timing_from_dt() argument
991 tegra_emc_load_timings_from_dt(struct tegra_emc * emc,struct device_node * node) tegra_emc_load_timings_from_dt() argument
1049 tegra_emc_rate_requests_init(struct tegra_emc * emc) tegra_emc_rate_requests_init() argument
1059 emc_request_rate(struct tegra_emc * emc,unsigned long new_min_rate,unsigned long new_max_rate,enum emc_rate_request_type type) emc_request_rate() argument
1100 emc_set_min_rate(struct tegra_emc * emc,unsigned long rate,enum emc_rate_request_type type) emc_set_min_rate() argument
1113 emc_set_max_rate(struct tegra_emc * emc,unsigned long rate,enum emc_rate_request_type type) emc_set_max_rate() argument
1151 tegra_emc_validate_rate(struct tegra_emc * emc,unsigned long rate) tegra_emc_validate_rate() argument
1165 struct tegra_emc *emc = s->private; tegra_emc_debug_available_rates_show() local
1183 struct tegra_emc *emc = data; tegra_emc_debug_min_rate_get() local
1192 struct tegra_emc *emc = data; tegra_emc_debug_min_rate_set() local
1213 struct tegra_emc *emc = data; tegra_emc_debug_max_rate_get() local
1222 struct tegra_emc *emc = data; tegra_emc_debug_max_rate_set() local
1241 emc_debugfs_init(struct device * dev,struct tegra_emc * emc) emc_debugfs_init() argument
1318 struct tegra_emc *emc = to_tegra_emc_provider(dst->provider); emc_icc_set() local
1342 tegra_emc_interconnect_init(struct tegra_emc * emc) tegra_emc_interconnect_init() argument
1395 tegra_emc_opp_table_init(struct tegra_emc * emc) tegra_emc_opp_table_init() argument
1445 struct tegra_emc *emc; tegra_emc_probe() local
[all...]
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dnvidia,tegra124-emc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The EMC interfaces with the off-chip SDRAM to service the request stream
19 const: nvidia,tegra124-emc
26 - description: external memory clock
28 clock-names:
[all …]
H A Dnvidia,tegra30-emc.yaml1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
15 The EMC interfaces with the off-chip SDRAM to service the request stream
16 sent from Memory Controller. The EMC also has various performance-affecting
18 settings. Tegra30 EMC supports multiple JEDEC standard protocols: LPDDR2,
[all …]
H A Dnvidia,tegra124-mc.yaml1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 Tegra124 SoC features a hybrid 2x32-bit / 1x64-bit memory controller.
22 const: nvidia,tegra124-mc
30 clock-names:
32 - const: mc
[all …]
H A Dnvidia,tegra30-mc.yaml1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
39 const: nvidia,tegra30-mc
47 clock-names:
49 - const: mc
[all …]
/linux/drivers/clk/tegra/
H A Dclk-tegra124-emc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/clk/tegra/clk-emc.c
11 #include <linux/clk-provider.h>
47 * List of clock sources for various parents the EMC clock can have.
79 struct tegra_emc *emc; member
82 struct emc_timing *timings; member
105 val = readl(tegra->clk_regs + CLK_SOURCE_EMC); in emc_recalc_rate()
113 * safer since things have EMC rate floors. Also don't touch parent_rate
125 for (k = 0; k < tegra->num_timings; k++) { in emc_determine_rate()
126 if (tegra->timings[k].ram_code == ram_code) in emc_determine_rate()
[all …]
H A Dclk-tegra210-emc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.
8 #include <linux/clk-provider.h>
53 struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw); in tegra210_clk_emc_get_parent() local
57 value = readl_relaxed(emc->regs + CLK_SOURCE_EMC); in tegra210_clk_emc_get_parent()
66 struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw); in tegra210_clk_emc_recalc_rate() local
71 * ->set_rate(), so the parent rate passed in here was cached from the in tegra210_clk_emc_recalc_rate()
72 * parent before the ->set_rate() call. in tegra210_clk_emc_recalc_rate()
74 * This can lead to wrong results being reported for the EMC clock if in tegra210_clk_emc_recalc_rate()
75 * the parent and/or parent rate have changed as part of the EMC rate in tegra210_clk_emc_recalc_rate()
[all …]
/linux/arch/arm/boot/dts/nvidia/
H A Dtegra30-asus-nexus7-tilapia-memory-timings.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include "tegra30-asus-nexus7-grouper-memory-timings.dtsi"
7 * Tilapia's memory timings are pretty much the same as the Grouper's
9 * these differentiating timings are overridden here for Tilapia.
12 memory-controller@7000f400 {
13 emc-timings-0 {
14 timing-667000000 {
15 clock-frequency = <667000000>;
17 nvidia,emc-auto-cal-interval = <0x001fffff>;
18 nvidia,emc-mode-1 = <0x80100002>;
[all …]
H A Dtegra30-asus-tf201.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-asus-transformer-common.dtsi"
5 #include "tegra30-asus-lvds-display.dtsi"
19 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
27 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
35 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
43 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
51 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
57 /* Azurewave AW-NH615 BCM4329B1 */
[all …]
H A Dtegra30-asus-tf300t.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-asus-transformer-common.dtsi"
5 #include "tegra30-asus-lvds-display.dtsi"
12 tf300t-init-hog {
13 gpio-hog;
15 output-low;
27 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
35 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
43 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
[all …]
H A Dtegra30-asus-tf300tg.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-asus-transformer-common.dtsi"
5 #include "tegra30-asus-lvds-display.dtsi"
12 tf300tg-init-hog {
13 gpio-hog;
28 output-low;
39 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
47 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
55 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
[all …]
H A Dtegra30-asus-tf700t.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-asus-transformer-common.dtsi"
20 remote-endpoint = <&bridge_input>;
21 bus-width = <24>;
36 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
44 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
52 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
60 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
68 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
[all …]
H A Dtegra30-lg-p880.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-lg-x3.dtsi"
16 pinctrl-names = "default";
17 pinctrl-0 = <&state_default>;
21 host-wlan-wake {
26 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
29 /* GNSS UART-B pinmux */
30 uartb-rxd {
35 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
[all …]
H A Dtegra30-lg-p895.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-lg-x3.dtsi"
11 pinctrl-names = "default";
12 pinctrl-0 = <&state_default>;
15 /* GNSS UART-B pinmux */
16 uartb-cts-rxd {
22 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
24 uartb-rts-txd {
30 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
[all …]
H A Dtegra30-pegatron-chagall.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/gpio-keys.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/thermal/thermal.h>
9 #include "tegra30-cpu-opp.dtsi"
10 #include "tegra30-cpu-opp-microvolt.dtsi"
11 #include "tegra30-asus-lvds-display.dtsi"
16 chassis-type = "tablet";
35 * pre-existing /chosen node to be available to insert the
[all …]
H A Dtegra124-nyan-blaze-emc.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra124-car.h>
7 emc-timings-1 {
8 nvidia,ram-code = <1>;
10 timing-12750000 {
11 clock-frequency = <12750000>;
12 nvidia,parent-clock-frequency = <408000000>;
14 clock-names = "emc-parent";
17 timing-20400000 {
18 clock-frequency = <20400000>;
[all …]
H A Dtegra124-apalis-emc.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR X11
3 * Copyright 2016-2019 Toradex AG
7 #include <dt-bindings/clock/tegra124-car.h>
11 emc-timings-1 {
12 nvidia,ram-code = <1>;
14 timing-12750000 {
15 clock-frequency = <12750000>;
16 nvidia,parent-clock-frequency = <408000000>;
18 clock-names = "emc-parent";
21 timing-20400000 {
[all …]
H A Dtegra124-jetson-tk1-emc.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra124-car.h>
7 emc-timings-3 {
8 nvidia,ram-code = <3>;
10 timing-12750000 {
11 clock-frequency = <12750000>;
12 nvidia,parent-clock-frequency = <408000000>;
14 clock-names = "emc-parent";
17 timing-20400000 {
18 clock-frequency = <20400000>;
[all …]
H A Dtegra30-asus-nexus7-grouper-memory-timings.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 memory-controller@7000f000 {
5 emc-timings-0 {
6 nvidia,ram-code = <0>; /* Elpida EDJ2108EDBG-DJL-F */
8 timing-25500000 {
9 clock-frequency = <25500000>;
11 nvidia,emem-configuration = <
33 timing-51000000 {
34 clock-frequency = <51000000>;
36 nvidia,emem-configuration = <
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dnvidia,tegra124-car.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/nvidia,tegra124-car.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
31 - nvidia,tegra124-car
32 - nvidia,tegra132-car
37 '#clock-cells':
40 "#reset-cells":
[all …]

12