Lines Matching +full:emc +full:- +full:timings +full:-
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The EMC interfaces with the off-chip SDRAM to service the request stream
19 const: nvidia,tegra124-emc
26 - description: external memory clock
28 clock-names:
30 - const: emc
32 "#interconnect-cells":
35 nvidia,memory-controller:
40 power-domains:
45 operating-points-v2:
47 Should contain freqs and voltages and opp-supported-hw property, which
51 "^emc-timings-[0-9]+$":
55 nvidia,ram-code:
62 "^timing-[0-9]+$":
65 clock-frequency:
71 nvidia,emc-auto-cal-config:
75 timings
77 nvidia,emc-auto-cal-config2:
81 timings
83 nvidia,emc-auto-cal-config3:
87 timings
89 nvidia,emc-auto-cal-interval:
96 nvidia,emc-bgbias-ctl0:
99 value of the EMC_BGBIAS_CTL0 register for this set of timings
101 nvidia,emc-cfg:
104 value of the EMC_CFG register for this set of timings
106 nvidia,emc-cfg-2:
109 value of the EMC_CFG_2 register for this set of timings
111 nvidia,emc-ctt-term-ctrl:
114 value of the EMC_CTT_TERM_CTRL register for this set of timings
116 nvidia,emc-mode-1:
119 value of the EMC_MRW register for this set of timings
121 nvidia,emc-mode-2:
124 value of the EMC_MRW2 register for this set of timings
126 nvidia,emc-mode-4:
129 value of the EMC_MRW4 register for this set of timings
131 nvidia,emc-mode-reset:
134 reset value of the EMC_MRS register for this set of timings
136 nvidia,emc-mrs-wait-cnt:
139 value of the EMR_MRS_WAIT_CNT register for this set of timings
141 nvidia,emc-sel-dpd-ctrl:
144 value of the EMC_SEL_DPD_CTRL register for this set of timings
146 nvidia,emc-xm2dqspadctrl2:
149 value of the EMC_XM2DQSPADCTRL2 register for this set of timings
151 nvidia,emc-zcal-cnt-long:
153 number of EMC clocks to wait before issuing any commands after
159 nvidia,emc-zcal-interval:
162 value of the EMC_ZCAL_INTERVAL register for this set of timings
164 nvidia,emc-configuration:
166 EMC timing characterization data. These are the registers (see
167 section "15.6.2 EMC Registers" in the TRM) whose values need to
169 $ref: /schemas/types.yaml#/definitions/uint32-array
171 - description: EMC_RC
172 - description: EMC_RFC
173 - description: EMC_RFC_SLR
174 - description: EMC_RAS
175 - description: EMC_RP
176 - description: EMC_R2W
177 - description: EMC_W2R
178 - description: EMC_R2P
179 - description: EMC_W2P
180 - description: EMC_RD_RCD
181 - description: EMC_WR_RCD
182 - description: EMC_RRD
183 - description: EMC_REXT
184 - description: EMC_WEXT
185 - description: EMC_WDV
186 - description: EMC_WDV_MASK
187 - description: EMC_QUSE
188 - description: EMC_QUSE_WIDTH
189 - description: EMC_IBDLY
190 - description: EMC_EINPUT
191 - description: EMC_EINPUT_DURATION
192 - description: EMC_PUTERM_EXTRA
193 - description: EMC_PUTERM_WIDTH
194 - description: EMC_PUTERM_ADJ
195 - description: EMC_CDB_CNTL_1
196 - description: EMC_CDB_CNTL_2
197 - description: EMC_CDB_CNTL_3
198 - description: EMC_QRST
199 - description: EMC_QSAFE
200 - description: EMC_RDV
201 - description: EMC_RDV_MASK
202 - description: EMC_REFRESH
203 - description: EMC_BURST_REFRESH_NUM
204 - description: EMC_PRE_REFRESH_REQ_CNT
205 - description: EMC_PDEX2WR
206 - description: EMC_PDEX2RD
207 - description: EMC_PCHG2PDEN
208 - description: EMC_ACT2PDEN
209 - description: EMC_AR2PDEN
210 - description: EMC_RW2PDEN
211 - description: EMC_TXSR
212 - description: EMC_TXSRDLL
213 - description: EMC_TCKE
214 - description: EMC_TCKESR
215 - description: EMC_TPD
216 - description: EMC_TFAW
217 - description: EMC_TRPAB
218 - description: EMC_TCLKSTABLE
219 - description: EMC_TCLKSTOP
220 - description: EMC_TREFBW
221 - description: EMC_FBIO_CFG6
222 - description: EMC_ODT_WRITE
223 - description: EMC_ODT_READ
224 - description: EMC_FBIO_CFG5
225 - description: EMC_CFG_DIG_DLL
226 - description: EMC_CFG_DIG_DLL_PERIOD
227 - description: EMC_DLL_XFORM_DQS0
228 - description: EMC_DLL_XFORM_DQS1
229 - description: EMC_DLL_XFORM_DQS2
230 - description: EMC_DLL_XFORM_DQS3
231 - description: EMC_DLL_XFORM_DQS4
232 - description: EMC_DLL_XFORM_DQS5
233 - description: EMC_DLL_XFORM_DQS6
234 - description: EMC_DLL_XFORM_DQS7
235 - description: EMC_DLL_XFORM_DQS8
236 - description: EMC_DLL_XFORM_DQS9
237 - description: EMC_DLL_XFORM_DQS10
238 - description: EMC_DLL_XFORM_DQS11
239 - description: EMC_DLL_XFORM_DQS12
240 - description: EMC_DLL_XFORM_DQS13
241 - description: EMC_DLL_XFORM_DQS14
242 - description: EMC_DLL_XFORM_DQS15
243 - description: EMC_DLL_XFORM_QUSE0
244 - description: EMC_DLL_XFORM_QUSE1
245 - description: EMC_DLL_XFORM_QUSE2
246 - description: EMC_DLL_XFORM_QUSE3
247 - description: EMC_DLL_XFORM_QUSE4
248 - description: EMC_DLL_XFORM_QUSE5
249 - description: EMC_DLL_XFORM_QUSE6
250 - description: EMC_DLL_XFORM_QUSE7
251 - description: EMC_DLL_XFORM_ADDR0
252 - description: EMC_DLL_XFORM_ADDR1
253 - description: EMC_DLL_XFORM_ADDR2
254 - description: EMC_DLL_XFORM_ADDR3
255 - description: EMC_DLL_XFORM_ADDR4
256 - description: EMC_DLL_XFORM_ADDR5
257 - description: EMC_DLL_XFORM_QUSE8
258 - description: EMC_DLL_XFORM_QUSE9
259 - description: EMC_DLL_XFORM_QUSE10
260 - description: EMC_DLL_XFORM_QUSE11
261 - description: EMC_DLL_XFORM_QUSE12
262 - description: EMC_DLL_XFORM_QUSE13
263 - description: EMC_DLL_XFORM_QUSE14
264 - description: EMC_DLL_XFORM_QUSE15
265 - description: EMC_DLI_TRIM_TXDQS0
266 - description: EMC_DLI_TRIM_TXDQS1
267 - description: EMC_DLI_TRIM_TXDQS2
268 - description: EMC_DLI_TRIM_TXDQS3
269 - description: EMC_DLI_TRIM_TXDQS4
270 - description: EMC_DLI_TRIM_TXDQS5
271 - description: EMC_DLI_TRIM_TXDQS6
272 - description: EMC_DLI_TRIM_TXDQS7
273 - description: EMC_DLI_TRIM_TXDQS8
274 - description: EMC_DLI_TRIM_TXDQS9
275 - description: EMC_DLI_TRIM_TXDQS10
276 - description: EMC_DLI_TRIM_TXDQS11
277 - description: EMC_DLI_TRIM_TXDQS12
278 - description: EMC_DLI_TRIM_TXDQS13
279 - description: EMC_DLI_TRIM_TXDQS14
280 - description: EMC_DLI_TRIM_TXDQS15
281 - description: EMC_DLL_XFORM_DQ0
282 - description: EMC_DLL_XFORM_DQ1
283 - description: EMC_DLL_XFORM_DQ2
284 - description: EMC_DLL_XFORM_DQ3
285 - description: EMC_DLL_XFORM_DQ4
286 - description: EMC_DLL_XFORM_DQ5
287 - description: EMC_DLL_XFORM_DQ6
288 - description: EMC_DLL_XFORM_DQ7
289 - description: EMC_XM2CMDPADCTRL
290 - description: EMC_XM2CMDPADCTRL4
291 - description: EMC_XM2CMDPADCTRL5
292 - description: EMC_XM2DQPADCTRL2
293 - description: EMC_XM2DQPADCTRL3
294 - description: EMC_XM2CLKPADCTRL
295 - description: EMC_XM2CLKPADCTRL2
296 - description: EMC_XM2COMPPADCTRL
297 - description: EMC_XM2VTTGENPADCTRL
298 - description: EMC_XM2VTTGENPADCTRL2
299 - description: EMC_XM2VTTGENPADCTRL3
300 - description: EMC_XM2DQSPADCTRL3
301 - description: EMC_XM2DQSPADCTRL4
302 - description: EMC_XM2DQSPADCTRL5
303 - description: EMC_XM2DQSPADCTRL6
304 - description: EMC_DSR_VTTGEN_DRV
305 - description: EMC_TXDSRVTTGEN
306 - description: EMC_FBIO_SPARE
307 - description: EMC_ZCAL_WAIT_CNT
308 - description: EMC_MRS_WAIT_CNT2
309 - description: EMC_CTT
310 - description: EMC_CTT_DURATION
311 - description: EMC_CFG_PIPE
312 - description: EMC_DYN_SELF_REF_CONTROL
313 - description: EMC_QPOP
316 - clock-frequency
317 - nvidia,emc-auto-cal-config
318 - nvidia,emc-auto-cal-config2
319 - nvidia,emc-auto-cal-config3
320 - nvidia,emc-auto-cal-interval
321 - nvidia,emc-bgbias-ctl0
322 - nvidia,emc-cfg
323 - nvidia,emc-cfg-2
324 - nvidia,emc-ctt-term-ctrl
325 - nvidia,emc-mode-1
326 - nvidia,emc-mode-2
327 - nvidia,emc-mode-4
328 - nvidia,emc-mode-reset
329 - nvidia,emc-mrs-wait-cnt
330 - nvidia,emc-sel-dpd-ctrl
331 - nvidia,emc-xm2dqspadctrl2
332 - nvidia,emc-zcal-cnt-long
333 - nvidia,emc-zcal-interval
334 - nvidia,emc-configuration
339 - compatible
340 - reg
341 - clocks
342 - clock-names
343 - nvidia,memory-controller
344 - "#interconnect-cells"
345 - operating-points-v2
350 - |
351 #include <dt-bindings/clock/tegra124-car.h>
352 #include <dt-bindings/interrupt-controller/arm-gic.h>
354 mc: memory-controller@70019000 {
355 compatible = "nvidia,tegra124-mc";
358 clock-names = "mc";
362 #iommu-cells = <1>;
363 #reset-cells = <1>;
364 #interconnect-cells = <1>;
367 external-memory-controller@7001b000 {
368 compatible = "nvidia,tegra124-emc";
371 clock-names = "emc";
373 nvidia,memory-controller = <&mc>;
374 operating-points-v2 = <&dvfs_opp_table>;
375 power-domains = <&domain>;
377 #interconnect-cells = <0>;
379 emc-timings-0 {
380 nvidia,ram-code = <3>;
382 timing-0 {
383 clock-frequency = <12750000>;
385 nvidia,emc-auto-cal-config = <0xa1430000>;
386 nvidia,emc-auto-cal-config2 = <0x00000000>;
387 nvidia,emc-auto-cal-config3 = <0x00000000>;
388 nvidia,emc-auto-cal-interval = <0x001fffff>;
389 nvidia,emc-bgbias-ctl0 = <0x00000008>;
390 nvidia,emc-cfg = <0x73240000>;
391 nvidia,emc-cfg-2 = <0x000008c5>;
392 nvidia,emc-ctt-term-ctrl = <0x00000802>;
393 nvidia,emc-mode-1 = <0x80100003>;
394 nvidia,emc-mode-2 = <0x80200008>;
395 nvidia,emc-mode-4 = <0x00000000>;
396 nvidia,emc-mode-reset = <0x80001221>;
397 nvidia,emc-mrs-wait-cnt = <0x000e000e>;
398 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
399 nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
400 nvidia,emc-zcal-cnt-long = <0x00000042>;
401 nvidia,emc-zcal-interval = <0x00000000>;
403 nvidia,emc-configuration = <