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Searched +full:eloplus +full:- +full:dma +full:- +full:channel (Results 1 – 25 of 27) sorted by relevance

12

/linux/arch/powerpc/boot/dts/fsl/
H A Delo3-dma-0.dtsi2 * QorIQ Elo3 DMA device tree stub [ controller @ offset 0x100000 ]
35 dma0: dma@100300 {
36 #address-cells = <1>;
37 #size-cells = <1>;
38 compatible = "fsl,elo3-dma";
42 dma-channel@0 {
43 compatible = "fsl,eloplus-dma-channel";
47 dma-channel@80 {
48 compatible = "fsl,eloplus-dma-channel";
52 dma-channel@100 {
[all …]
H A Delo3-dma-1.dtsi2 * QorIQ Elo3 DMA device tree stub [ controller @ offset 0x101000 ]
35 dma1: dma@101300 {
36 #address-cells = <1>;
37 #size-cells = <1>;
38 compatible = "fsl,elo3-dma";
42 dma-channel@0 {
43 compatible = "fsl,eloplus-dma-channel";
47 dma-channel@80 {
48 compatible = "fsl,eloplus-dma-channel";
52 dma-channel@100 {
[all …]
H A Delo3-dma-2.dtsi2 * QorIQ Elo3 DMA device tree stub [ controller @ offset 0x102300 ]
35 dma2: dma@102300 {
36 #address-cells = <1>;
37 #size-cells = <1>;
38 compatible = "fsl,elo3-dma";
42 dma-channel@0 {
43 compatible = "fsl,eloplus-dma-channel";
47 dma-channel@80 {
48 compatible = "fsl,eloplus-dma-channel";
52 dma-channel@100 {
[all …]
H A Dpq3-dma-0.dtsi2 * PQ3 DMA device tree stub [ controller @ offset 0x21000 ]
35 dma@21300 {
36 #address-cells = <1>;
37 #size-cells = <1>;
38 compatible = "fsl,eloplus-dma";
41 cell-index = <0>;
42 dma-channel@0 {
43 compatible = "fsl,eloplus-dma-channel";
45 cell-index = <0>;
48 dma-channel@80 {
[all …]
H A Dpq3-dma-1.dtsi2 * PQ3 DMA device tree stub [ controller @ offset 0xc300 ]
35 dma@c300 {
36 #address-cells = <1>;
37 #size-cells = <1>;
38 compatible = "fsl,eloplus-dma";
41 cell-index = <1>;
42 dma-channel@0 {
43 compatible = "fsl,eloplus-dma-channel";
45 cell-index = <0>;
48 dma-channel@80 {
[all …]
H A Dqoriq-dma-0.dtsi2 * QorIQ DMA device tree stub [ controller @ offset 0x100000 ]
35 dma0: dma@100300 {
36 #address-cells = <1>;
37 #size-cells = <1>;
38 compatible = "fsl,eloplus-dma";
41 cell-index = <0>;
42 dma-channel@0 {
43 compatible = "fsl,eloplus-dma-channel";
45 cell-index = <0>;
48 dma-channel@80 {
[all …]
H A Dqoriq-dma-1.dtsi2 * QorIQ DMA device tree stub [ controller @ offset 0x101000 ]
35 dma1: dma@101300 {
36 #address-cells = <1>;
37 #size-cells = <1>;
38 compatible = "fsl,eloplus-dma";
41 cell-index = <1>;
42 dma-channel@0 {
43 compatible = "fsl,eloplus-dma-channel";
45 cell-index = <0>;
48 dma-channel@80 {
[all …]
H A Dmpc8641si-post.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2016 Elettra-Sincrotrone Trieste S.C.p.A.
9 #address-cells = <2>;
10 #size-cells = <1>;
11 compatible = "fsl,mpc8641-localbus", "simple-bus";
16 #address-cells = <1>;
17 #size-cells = <1>;
19 compatible = "fsl,mpc8641-soc", "simple-bus";
20 bus-frequency = <0>;
22 mcm-law@0 {
[all …]
/linux/arch/powerpc/boot/dts/
H A Dxcalibur1501.dts1 // SPDX-License-Identifier: GPL-2.0-only
6 * XCalibur1501 6U CompactPCI single-board computer based on MPC8572E
9 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
27 #address-cells = <1>;
28 #size-cells = <0>;
33 d-cache-line-size = <32>; // 32 bytes
34 i-cache-line-size = <32>; // 32 bytes
35 d-cache-size = <0x8000>; // L1, 32K
[all …]
H A Dxpedite5301.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
15 form-factor = "PMC/XMC";
16 boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
28 #address-cells = <1>;
29 #size-cells = <0>;
34 d-cache-line-size = <32>; // 32 bytes
35 i-cache-line-size = <32>; // 32 bytes
[all …]
H A Dxpedite5370.dts1 // SPDX-License-Identifier: GPL-2.0-only
6 * XPedite5370 3U VPX single-board computer based on MPC8572E
9 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
26 #address-cells = <1>;
27 #size-cells = <0>;
32 d-cache-line-size = <32>; // 32 bytes
33 i-cache-line-size = <32>; // 32 bytes
34 d-cache-size = <0x8000>; // L1, 32K
[all …]
H A Dxpedite5330.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
15 form-factor = "3U CompactPCI";
16 boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
29 #address-cells = <1>;
30 #size-cells = <0>;
33 cell-index = <0>;
37 * module-present;
[all …]
H A Dstx_gp3_8560.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * STX GP3 - 8560 ADS Device Tree Source
8 /dts-v1/;
14 compatible = "stx,gp3-8560", "stx,gp3";
15 #address-cells = <1>;
16 #size-cells = <1>;
26 #address-cells = <1>;
27 #size-cells = <0>;
32 d-cache-line-size = <32>;
33 i-cache-line-size = <32>;
[all …]
H A Dtqm8541.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
15 #address-cells = <1>;
16 #size-cells = <1>;
27 #address-cells = <1>;
28 #size-cells = <0>;
33 d-cache-line-size = <32>;
34 i-cache-line-size = <32>;
35 d-cache-size = <32768>;
36 i-cache-size = <32768>;
[all …]
H A Dtqm8555.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
15 #address-cells = <1>;
16 #size-cells = <1>;
27 #address-cells = <1>;
28 #size-cells = <0>;
33 d-cache-line-size = <32>;
34 i-cache-line-size = <32>;
35 d-cache-size = <32768>;
36 i-cache-size = <32768>;
[all …]
H A Dksi8560.dts15 /dts-v1/;
22 #address-cells = <1>;
23 #size-cells = <1>;
32 #address-cells = <1>;
33 #size-cells = <0>;
38 d-cache-line-size = <32>;
39 i-cache-line-size = <32>;
40 d-cache-size = <0x8000>; /* L1, 32K */
41 i-cache-size = <0x8000>; /* L1, 32K */
42 timebase-frequency = <0>; /* From U-boot */
[all …]
H A Dtqm8540.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
15 #address-cells = <1>;
16 #size-cells = <1>;
28 #address-cells = <1>;
29 #size-cells = <0>;
34 d-cache-line-size = <32>;
35 i-cache-line-size = <32>;
36 d-cache-size = <32768>;
37 i-cache-size = <32768>;
[all …]
H A Dtqm8560.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
9 /dts-v1/;
16 #address-cells = <1>;
17 #size-cells = <1>;
29 #address-cells = <1>;
30 #size-cells = <0>;
35 d-cache-line-size = <32>;
36 i-cache-line-size = <32>;
37 d-cache-size = <32768>;
38 i-cache-size = <32768>;
[all …]
H A Dstxssa8555.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * MPC8555-based STx GP3 Device Tree Source
10 /dts-v1/;
16 compatible = "stx,gp3-8560", "stx,gp3";
17 #address-cells = <1>;
18 #size-cells = <1>;
29 #address-cells = <1>;
30 #size-cells = <0>;
35 d-cache-line-size = <32>; // 32 bytes
36 i-cache-line-size = <32>; // 32 bytes
[all …]
H A Dxpedite5200.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
29 #address-cells = <1>;
30 #size-cells = <0>;
35 d-cache-line-size = <32>; // 32 bytes
36 i-cache-line-size = <32>; // 32 bytes
37 d-cache-size = <0x8000>; // L1, 32K
38 i-cache-size = <0x8000>; // L1, 32K
[all …]
H A Dtqm8548.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
9 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
30 #address-cells = <1>;
31 #size-cells = <0>;
36 d-cache-line-size = <32>; // 32 bytes
37 i-cache-line-size = <32>; // 32 bytes
38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000>; // L1, 32K
[all …]
H A Dtqm8548-bigflash.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
9 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
30 #address-cells = <1>;
31 #size-cells = <0>;
36 d-cache-line-size = <32>; // 32 bytes
37 i-cache-line-size = <32>; // 32 bytes
38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000>; // L1, 32K
[all …]
H A Dxpedite5200_xmon.dts1 // SPDX-License-Identifier: GPL-2.0-only
7 * xMon boot loader memory map which differs from U-Boot's.
10 /dts-v1/;
15 #address-cells = <1>;
16 #size-cells = <1>;
17 form-factor = "PMC/XMC";
18 boot-bank = <0x0>;
33 #address-cells = <1>;
34 #size-cells = <0>;
39 d-cache-line-size = <32>; // 32 bytes
[all …]
/linux/Documentation/devicetree/bindings/sound/
H A Dfsl,ssi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shengjiu Wang <shengjiu.wang@nxp.com>
13 Notes on fsl,playback-dma and fsl,capture-dma
14 On SOCs that have an SSI, specific DMA channels are hard-wired for playback
15 and capture. On the MPC8610, for example, SSI1 must use DMA channel 0 for
16 playback and DMA channel 1 for capture. SSI2 must use DMA channel 2 for
17 playback and DMA channel 3 for capture. The developer can choose which
18 DMA controller to use, but the channels themselves are hard-wired. The
[all …]
/linux/arch/powerpc/platforms/85xx/
H A Dcommon.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Routines common to most mpc85xx-based boards.
21 { .compatible = "simple-bus", },
28 /* So that the DMA channel nodes can be probed individually: */
29 { .compatible = "fsl,eloplus-dma", },
31 { .compatible = "fsl,mpc8548-guts", },
33 { .compatible = "gpio-leds", },
35 { .compatible = "fsl,mpc8540-pci", },
36 { .compatible = "fsl,mpc8548-pcie", },
37 { .compatible = "fsl,p1022-pcie", },
[all …]

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