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/linux/tools/perf/pmu-events/arch/powerpc/power8/
H A D	cache.json	6 …p's L2 or L3 on a different Node or Group (Distant), as this chip due to either only demand loads … 12 …p's L2 or L3 on a different Node or Group (Distant), as this chip due to either only demand loads … 18 …ded from another chip's L4 on a different Node or Group (Distant) due to either only demand loads … 24 …n": "The processor's data cache was reloaded from local core's L2 due to either only demand loads … 36 …cache was reloaded from a location other than the local core's L2 due to either only demand loads … 42 …he was reloaded from local core's L2 with load hit store conflict due to either only demand loads … 48 …ta cache was reloaded from local core's L2 with dispatch conflict due to either only demand loads … 54 …from local core's L2 hit without dispatch conflicts on Mepf state due to either only demand loads … 60 …r's data cache was reloaded from local core's L2 without conflict due to either only demand loads … 66 …n": "The processor's data cache was reloaded from local core's L3 due to either only demand loads … [all …]
H A D	frontend.json	90 …p's L2 or L3 on a different Node or Group (Distant), as this chip due to either an instruction fet… 96 …p's L2 or L3 on a different Node or Group (Distant), as this chip due to either an instruction fet… 102 …ded from another chip's L4 on a different Node or Group (Distant) due to either an instruction fet… 108 …ed from another chip's memory on the same Node or Group (Distant) due to either an instruction fet… 114 …e processor's Instruction cache was reloaded from local core's L2 due to either an instruction fet… 120 …cache was reloaded from a location other than the local core's L2 due to either an instruction fet… 126 …he was reloaded from local core's L2 with load hit store conflict due to either an instruction fet… 132 …on cache was reloaded from local core's L2 with dispatch conflict due to either an instruction fet… 138 …rom local core's L2 hit without dispatch conflicts on Mepf state. due to either an instruction fet… 144 …truction cache was reloaded from local core's L2 without conflict due to either an instruction fet… [all …]
H A D	other.json	35 …"BriefDescription": "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump … 65 …"BriefDescription": "Final Pump Scope (system) mispredicted. Either the original scope was too sma… 365 …"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for either de… 371 …p's L2 or L3 on a different Node or Group (Distant), as this chip due to either demand loads or da… 372 …p's L2 or L3 on a different Node or Group (Distant), as this chip due to either only demand loads … 377 …p's L2 or L3 on a different Node or Group (Distant), as this chip due to either demand loads or da… 378 …p's L2 or L3 on a different Node or Group (Distant), as this chip due to either only demand loads … 383 …ded from another chip's L4 on a different Node or Group (Distant) due to either demand loads or da… 384 …ded from another chip's L4 on a different Node or Group (Distant) due to either only demand loads … 389 …ed from another chip's memory on the same Node or Group (Distant) due to either demand loads or da… [all …]
H A D	memory.json	18 …ed from another chip's memory on the same Node or Group (Distant) due to either only demand loads … 24 … processor's data cache was reloaded from the local chip's Memory due to either only demand loads … 30 … from a memory location including L4 from local remote or distant due to either only demand loads … 36 …loaded from another chip's L4 on the same Node or Group ( Remote) due to either only demand loads … 42 …ed from another chip's memory on the same Node or Group ( Remote) due to either only demand loads … 53 …"BriefDescription": "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump … 83 …"BriefDescription": "Final Pump Scope (system) mispredicted. Either the original scope was too sma… 119 …"BriefDescription": "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump … 203 …"BriefDescription": "Final Pump Scope (system) mispredicted. Either the original scope was too sma…
/linux/drivers/firmware/xilinx/
H A D	zynqmp.c	139 * Return: Returns status, either success or error+reason 182 * Return: Returns status, either success or error+reason 295 * Return: Returns status, either success or error+reason 316 * Return: Returns status, either success or error+reason 374 * Return: Returns status, either success or error+reason 438 * Return: Returns status, either success or error+reason 493 * Return: Returns status, either success or error+reason 543 * Return: Returns status, either success or error+reason 563 * Return: Returns status, either success or error+reason 592 * Return: Returns status, either success or error+reason [all …]
/linux/Documentation/ABI/testing/
H A D	sysfs-platform-msi-laptop	`13 Enable automatic brightness control: contains either 0 or 1. If 22 WLAN subsystem enabled: contains either 0 or 1. 29 Bluetooth subsystem enabled: contains either 0 or 1. Please 38 Contains either 0 or 1 and indicates if touchpad is turned on. 46 Contains either 0 or 1 and indicates if turbo mode is turned 59 Contains either 0 or 1 and indicates if ECO mode is turned on. 80 Contains either 0 or 1 and indicates if fan speed is controlled`
/linux/tools/perf/pmu-events/arch/x86/amdzen5/
H A D	load-store.json	114 "BriefDescription": "Demand data cache fills from either DRAM or MMIO in the same NUMA node.", 132 …"BriefDescription": "Demand data cache fills from either DRAM or MMIO in a different NUMA node (sa… 138 …"BriefDescription": "Demand data cache fills from either DRAM or MMIO in the same or a different N… 144 …"BriefDescription": "Demand data cache fills from either cache of another CCX, DRAM or MMIO when t… 186 "BriefDescription": "Any data cache fills from either DRAM or MMIO in the same NUMA node.", 204 …"BriefDescription": "Any data cache fills from either DRAM or MMIO in a different NUMA node (same … 210 …"BriefDescription": "Any data cache fills from either DRAM or MMIO in any NUMA node (same or diffe… 216 …"BriefDescription": "Any data cache fills from either cache of another CCX, DRAM or MMIO when the … 378 …"BriefDescription": "Software prefetch data cache fills from either DRAM or MMIO in the same NUMA … 396 …"BriefDescription": "Software prefetch data cache fills from either DRAM or MMIO in a different NU… [all …]
/linux/tools/perf/pmu-events/arch/x86/amdzen6/
H A D	load-store.json	120 …"BriefDescription": "Demand data cache fills where data is returned from either DRAM or MMIO in th… 138 …"BriefDescription": "Demand data cache fills where data is returned from either DRAM or MMIO in a … 144 …"BriefDescription": "Demand data cache fills where data is returned from either DRAM or MMIO in th… 150 …"BriefDescription": "Demand data cache fills where data is returned from either cache of another C… 192 …"BriefDescription": "Any data cache fills where data is returned from either DRAM or MMIO in the s… 210 …"BriefDescription": "Any data cache fills where data is returned from either DRAM or MMIO in a dif… 216 …"BriefDescription": "Any data cache fills where data is returned from either DRAM or MMIO in the s… 222 …"BriefDescription": "Any data cache fills where data is returned from either cache of another CCX,… 384 …"BriefDescription": "Software prefetch data cache fills where data is returned from either DRAM or… 402 …"BriefDescription": "Software prefetch data cache fills where data is returned from either DRAM or… [all …]
H A D	inst-cache.json	`75 …"BriefDescription": "Instruction cache fills where data is returned from either DRAM or MMIO in th… 93 …"BriefDescription": "Instruction cache fills where data is returned from either DRAM or MMIO in a … 99 …"BriefDescription": "Instruction cache fills where data is returned from either DRAM or MMIO in th… 105 …"BriefDescription": "Instruction cache fills where data is returned from either cache of another C…`
/linux/tools/testing/selftests/bpf/progs/
H A D	verifier_var_off.c	25 /* add it to skb. We now have either &skb->len or\ in variable_offset_ctx_access() 51 /* add it to fp. We now have either fp-4 or fp-8, but\ in stack_read_priv_vs_unpriv() 74 /* add it to fp. We now have either fp-4 or fp-8, but\ in variable_offset_stack_read_uninitialized() 105 /* Add it to fp. We now have either fp-8 or \ in stack_write_priv_vs_unpriv() 143 /* Add it to fp. We now have either fp-8 or fp-16, but\ in stack_write_followed_by_read() 185 /* Add it to fp. We now have either fp-8 or fp-16, but\ in stack_write_clobbers_spilled_regs() 251 /* add it to fp. We now have either fp-4 or fp-8, but\ in access_max_out_of_bound() 309 /* add it to fp. We now have either fp-516 or fp-512, but\ in access_min_out_of_bound() 339 /* Add it to fp. We now have either fp-12 or fp-16, but we don't know\ in access_min_off_min_initialized() 372 /* Add it to fp. We now have either f in stack_access_priv_vs_unpriv() [all...]
/linux/tools/perf/pmu-events/arch/x86/jaketown/
H A D	uncore-io.json	17 … on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must fir… 27 … on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must fir… 37 … on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must fir… 47 …r of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credi… 57 …r of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credi… 67 …r of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credi… 77 … on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must fir… 87 … on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must fir… 97 … on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must fir…
/linux/arch/mips/include/asm/octeon/
H A D	cvmx-spi.h	`90 * active) or as a halfplex (either the Tx data path is 108 * active) or as a halfplex (either the Tx data path is 177 * active) or as a halfplex (either the Tx data path is 193 * active) or as a halfplex (either the Tx data path is 210 * active) or as a halfplex (either the Tx data path is 227 * active) or as a halfplex (either the Tx data path is 244 * active) or as a halfplex (either the Tx data path is 261 * active) or as a halfplex (either the Tx data path is`
/linux/tools/perf/pmu-events/arch/x86/sandybridge/
H A D	cache.json	664 …code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit… 714 …ch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the … 724 …data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit… 764 …ch code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the … 774 …code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit… 814 …ch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the … 824 …data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit… 864 …prefetch RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the … 874 …fetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit… 924 …d & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the … [all …]
/linux/Documentation/devicetree/bindings/iio/frequency/
H A D	adi,adrf6780.yaml	`55 Intermediate Frequency Mode Enable. Either IF Mode or I/Q Mode 61 I/Q Mode Enable. Either IF Mode or I/Q Mode can be enabled at a 68 Oscillator Input Frequency. Either LOx1 or LOx2 can be enabled 75 output frequency (LO x1). Either LOx1 or LOx2 can be enabled`
/linux/tools/perf/pmu-events/arch/powerpc/power10/
H A D	others.json	`45 …"BriefDescription": "Load instructions in LD0 port that are either unaligned, or treated as unalig… 50 …"BriefDescription": "Load instructions in LD1 port that are either unaligned, or treated as unalig… 55 …"BriefDescription": "Store instructions in ST0 port that are either unaligned, or treated as unali… 60 …"BriefDescription": "Store instructions in ST1 port that are either unaligned, or treated as unali…`
/linux/include/net/
H A D	mac802154.h	`163 * either zero or negative errno. Called with pib_lock held. 168 * Returns either zero, or negative errno. Called with pib_lock held. 173 * Returns either zero, or negative errno. 177 * Returns either zero, or negative errno. 182 * Returns either zero, or negative errno. 186 * Returns either zero, or negative errno. 191 * Returns either zero, or negative errno. 195 * Returns either zero, or negative errno. 199 * Returns either zero, or negative errno.`
/linux/arch/arm64/boot/dts/rockchip/
H A D	rk3588-jaguar-pre-ict-tester.dtso	`93 * either signals). 136 * either signals). 146 * either signals). 156 * either signals). 166 * either signals).`
/linux/arch/mips/kernel/
H A D	jump_label.c	`23 * - the ISA bit of the target, either 0 or 1 respectively, 26 * immediate field of the machine instruction, either 2 or 1, 29 * delay-slot instruction, either 256MB or 128MB, 31 * - the jump target alignment, either 4 or 2 bytes.`
/linux/Documentation/userspace-api/gpio/
H A D	sysfs.rst	`78 reads as either "in" or "out". This value may 90 reads as either 0 (inactive) or 1 (active). If the GPIO 101 zero. Alternatively, either lseek(2) to the beginning of the 106 reads as either "none", "rising", "falling", or 114 reads as either 0 (false) or 1 (true). Write`
/linux/drivers/clk/baikal-t1/
H A D	Kconfig	`26 signals, which are either directly wired to the consumers (like 37 SoC. CCU dividers can be either configurable or with fixed divider, 38 either gateable or ungateable. Some of the CCU dividers can be as well`
/linux/tools/perf/pmu-events/arch/x86/silvermont/
H A D	cache.json	151 … (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the … 201 … (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the … 241 … "Counts any request that miss L2 and the snoops to sibling cores hit in either E/S state and the … 291 … (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the … 351 …nstruction cacheline that miss L2 and the snoops to sibling cores hit in either E/S state and the … 411 …U prefetch data read that miss L2 and the snoops to sibling cores hit in either E/S state and the … 461 …nd DCU prefetch RFOs that miss L2 and the snoops to sibling cores hit in either E/S state and the … 541 …prefetcher data read that miss L2 and the snoops to sibling cores hit in either E/S state and the … 571 …ed by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the … 611 …ed by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the … [all …]
/linux/tools/perf/pmu-events/arch/x86/broadwellx/
H A D	uncore-io.json	53 … on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must fir… 63 … on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must fir… 73 … on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must fir… 83 … on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must fir… 93 … on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must fir… 103 … on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must fir…
/linux/tools/perf/pmu-events/arch/x86/haswellx/
H A D	uncore-io.json	53 … on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must fir… 63 … on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must fir… 73 … on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must fir… 83 … on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must fir… 93 … on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must fir… 103 … on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must fir…
/linux/tools/perf/pmu-events/arch/x86/broadwellde/
H A D	uncore-io.json	53 … on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must fir… 63 … on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must fir… 73 … on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must fir… 83 … on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must fir… 93 … on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must fir… 103 … on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must fir…
/linux/Documentation/scsi/
H A D	scsi_eh.rst	48 Once LLDD gets hold of a scmd, either the LLDD will complete the 121 will either be retried (if the number of retries is not exhausted) 143 the host either complete normally, fail and get added to eh_cmd_q, or 146 If all scmds either complete or fail, the number of in-flight scmds 247 either retry or error-finish (notify upper layer of failure) recovered 367 If STU succeeds and the sdev is either offline or ready, 419 flushes eh_done_q by either retrying or notifying upper 429 all failed scmds and either ready for new commands or offline. Also, 460 - Either scsi_queue_insert() or scsi_finish_command() is called on

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