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/linux/Documentation/devicetree/bindings/display/panel/
H A Dpanel-edp-legacy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/panel/panel-edp-legacy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Legacy eDP panels from before the "edp-panel" compatible
10 - Douglas Anderson <dianders@chromium.org>
13 This binding file is a collection of eDP panels from before the generic
14 "edp-panel" compatible was introduced. It is kept around to support old
15 dts files. The only reason one might add a new panel here instead of using
16 the generic "edp-panel" is if it needed to be used on an eDP controller
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H A Dpanel-edp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/panel/panel-edp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Probeable (via DP AUX / EDID) eDP Panels with simple poweron sequences
10 - Douglas Anderson <dianders@chromium.org>
13 This binding file can be used to indicate that an eDP panel is connected
14 to a Embedded DisplayPort AUX bus (see display/dp-aux-bus.yaml) without
15 actually specifying exactly what panel is connected. This is useful for
16 the case that more than one different panel could be connected to the
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H A Dsamsung,atna33xc20.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/panel/samsung,atna33xc20.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung 13.3" FHD (1920x1080 pixels) eDP AMOLED panel
10 - Douglas Anderson <dianders@chromium.org>
13 - $ref: panel-common.yaml#
18 # Samsung 13.3" FHD (1920x1080 pixels) eDP AMOLED panel
19 - const: samsung,atna33xc20
20 - items:
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/linux/drivers/gpu/drm/i915/display/
H A Dintel_dp_aux_backlight.c97 INTEL_DP_AUX_BACKLIGHT_AUTO = -1,
109 /* Intel EDP backlight callbacks */
114 struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder); in intel_dp_aux_supports_hdr_backlight()
115 struct drm_dp_aux *aux = &intel_dp->aux; in intel_dp_aux_supports_hdr_backlight()
116 struct intel_panel *panel = &connector->panel; in intel_dp_aux_supports_hdr_backlight() local
126 drm_dbg_kms(display->drm, in intel_dp_aux_supports_hdr_backlight()
128 connector->base.base.id, connector->base.name, in intel_dp_aux_supports_hdr_backlight()
140 * do not use Intel proprietary eDP backlight control if we in intel_dp_aux_supports_hdr_backlight()
141 * don't have this data in panel EDID. In case we find panel in intel_dp_aux_supports_hdr_backlight()
146 if (display->params.enable_dpcd_backlight != INTEL_DP_AUX_BACKLIGHT_FORCE_INTEL && in intel_dp_aux_supports_hdr_backlight()
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H A Dintel_bios.c60 * blocks have a 1-byte Block ID, 2-byte Block Size, and Block Size bytes of
93 return _get_blocksize(block_data - 3); in get_blocksize()
106 index += bdb->header_size; in find_raw_section()
107 total = bdb->bdb_size; in find_raw_section()
139 return block - bdb; in raw_block_offset()
154 list_for_each_entry(entry, &display->vbt.bdb_blocks, node) { in bdb_find_section()
155 if (entry->section_id == section_id) in bdb_find_section()
156 return entry->data + 3; in bdb_find_section()
214 if (ptrs->panel_name.table_size) in lfp_data_min_size()
215 size = max(size, ptrs->panel_name.offset + in lfp_data_min_size()
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H A Dintel_psr.c50 * DOC: Panel Self Refresh (PSR/SRD)
52 * Since Haswell Display controller supports Panel Self-Refresh on display
59 * Panel Self Refresh must be supported by both Hardware (source) and
60 * Panel (sink).
62 * PSR saves power by caching the framebuffer in the panel RFB, which allows us
66 * The implementation uses the hardware-based PSR support which automatically
67 * enters/exits self-refresh mode. The hardware takes care of sending the
70 * changes to know when to exit self-refresh mode again. Unfortunately that
75 * issues the self-refresh re-enable code is done from a work queue, which
83 * entry/exit allows the HW to enter a low-power state even when page flipping
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/linux/drivers/gpu/drm/gma500/
H A Dintel_bios.c1 // SPDX-License-Identifier: GPL-2.0-only
28 index += bdb->header_size; in find_section()
29 total = bdb->bdb_size; in find_section()
48 struct bdb_edp *edp; in parse_edp() local
53 edp = find_section(bdb, BDB_EDP); in parse_edp()
55 dev_priv->edp.bpp = 18; in parse_edp()
56 if (!edp) { in parse_edp()
57 if (dev_priv->edp.support) { in parse_edp()
58 DRM_DEBUG_KMS("No eDP BDB found but eDP panel supported, assume %dbpp panel color depth.\n", in parse_edp()
59 dev_priv->edp.bpp); in parse_edp()
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H A Dcdv_intel_dp.c45 * struct i2c_algo_dp_aux_data - driver interface structure for i2c over dp
65 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; in i2c_algo_dp_aux_transaction()
68 ret = (*algo_data->aux_ch)(adapter, mode, in i2c_algo_dp_aux_transaction()
85 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; in i2c_algo_dp_aux_address()
92 algo_data->address = address; in i2c_algo_dp_aux_address()
93 algo_data->running = true; in i2c_algo_dp_aux_address()
104 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; in i2c_algo_dp_aux_stop()
111 if (algo_data->running) { in i2c_algo_dp_aux_stop()
113 algo_data->running = false; in i2c_algo_dp_aux_stop()
119 * I2C link must be running or this returns -EIO
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/linux/Documentation/devicetree/bindings/display/bridge/
H A Dps8640.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MIPI DSI to eDP Video Format Converter
10 - Nicolas Boichat <drinkcat@chromium.org>
13 The PS8640 is a low power MIPI-to-eDP video format converter supporting
14 mobile devices with embedded panel resolutions up to 2048 x 1536. The
17 device outputs eDP v1.4, one or two lanes, at a link rate of up to
28 powerdown-gpios:
32 reset-gpios:
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H A Dtoshiba,tc358767.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Toshiba TC358767/TC358867/TC9595 DSI/DPI/eDP bridge
10 - Andrey Gusakov <andrey.gusakov@cogentembedded.com>
14 converts DSI/DPI to eDP/DP .
19 - items:
20 - enum:
21 - toshiba,tc358867
22 - toshiba,tc9595
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H A Danx6345.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analogix ANX6345 eDP Transmitter
10 - Torsten Duwe <duwe@lst.de>
13 The ANX6345 is an ultra-low power Full-HD eDP transmitter designed for
24 reset-gpios:
28 dvdd12-supply:
31 dvdd25-supply:
46 Video port for eDP output (panel or connector).
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/linux/arch/arm64/boot/dts/qcom/
H A Dsc7180-trogdor-parade-ps8640.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Google Trogdor dts fragment for the boards with Parade ps8640 edp bridge
8 #include <dt-bindings/gpio/gpio.h>
11 pp3300_brij_ps8640: pp3300-brij-ps8640-regulator {
12 compatible = "regulator-fixed";
14 regulator-name = "pp3300_brij_ps8640";
16 regulator-min-microvolt = <3300000>;
17 regulator-max-microvolt = <3300000>;
20 enable-active-high;
22 pinctrl-names = "default";
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H A Dsc7180-trogdor-ti-sn65dsi86.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Google Trogdor dts fragment for the boards with TI sn65dsi86 edp bridge
8 #include <dt-bindings/gpio/gpio.h>
17 off-on-delay-us = <500000>;
22 * extra power cycle of the touchscreen and eDP panel at bootup.
23 * This should help speed bootup because we have off-on-delay-us.
25 regulator-boot-on;
32 clock-frequency = <400000>;
37 pinctrl-names = "default";
38 pinctrl-0 = <&edp_brij_en>, <&edp_brij_irq>;
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/linux/drivers/gpu/drm/panel/
H A Dpanel-edp.c17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
46 * struct panel_delay - Describes delays for a simple panel.
52 * The time (in milliseconds) that it takes after powering the panel
56 * NOTE: on some old panel data this number appears to be much too big.
59 * hpd_absent. While that works, it's non-ideal.
68 * This is T3-max on eDP timing diagrams or the delay from power on
74 * @powered_on_to_enable: Time between panel powered on and enable.
77 * between when panel powered on and enable may begin.
79 * This is (T3+T4+T5+T6+T8)-min on eDP timing diagrams or after the
116 * This is not specified in a standard way on eDP timing diagrams.
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
6 Panel registration and lookup framework.
12 tristate "ABT Y030XX067A 320x480 LCD panel"
17 Y030XX067A 320x480 3.0" panel as found in the YLM RG-280M, RG-300
18 and RG-99 handheld gaming consoles.
21 tristate "ARM Versatile panel driver"
27 reference designs. The panel is detected using special registers
31 tristate "ASUS Z00T TM5P5 NT35596 panel"
37 NT35596 1080x1920 video mode panel as found in some Asus
45 Say Y here to enable support for the AUO A030JTN01 320x480 3.0" panel
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/linux/drivers/gpu/drm/amd/display/dc/link/protocols/
H A Dlink_edp_panel_control.c27 * This file implements retrieval and configuration of eDP panel features such
28 * as PSR and ABM and it also manages specs defined eDP panel power sequences.
43 link->ctx->logger
71 /*set edp panel mode in receiver*/ in dp_set_panel_mode()
93 link->panel_mode = panel_mode; in dp_set_panel_mode()
94 DC_LOG_DETECTION_DP_CAPS("Link: %d eDP panel mode supported: %d " in dp_set_panel_mode()
95 "eDP panel mode enabled: %d \n", in dp_set_panel_mode()
96 link->link_index, in dp_set_panel_mode()
97 link->dpcd_caps.panel_mode_edp, in dp_set_panel_mode()
107 if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) { in dp_get_panel_mode()
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/linux/drivers/gpu/drm/msm/dp/
H A Ddp_drm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
17 * msm_dp_bridge_detect - callback to determine if connector is connected
25 dp = to_dp_bridge(bridge)->msm_dp_display; in msm_dp_bridge_detect()
27 drm_dbg_dp(dp->drm_dev, "link_ready = %s\n", in msm_dp_bridge_detect()
28 (dp->link_ready) ? "true" : "false"); in msm_dp_bridge_detect()
30 return (dp->link_ready) ? connector_status_connected : in msm_dp_bridge_detect()
41 dp = to_dp_bridge(bridge)->msm_dp_display; in msm_dp_bridge_atomic_check()
43 drm_dbg_dp(dp->drm_dev, "link_ready = %s\n", in msm_dp_bridge_atomic_check()
44 (dp->link_ready) ? "true" : "false"); in msm_dp_bridge_atomic_check()
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H A Ddp_display.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
32 MODULE_PARM_DESC(psr_enabled, "enable PSR for eDP and DP displays");
91 struct msm_dp_panel *panel; member
173 { .compatible = "qcom,sa8775p-dp", .data = &msm_dp_desc_sa8775p },
174 { .compatible = "qcom,sc7180-dp", .data = &msm_dp_desc_sc7180 },
175 { .compatible = "qcom,sc7280-dp", .data = &msm_dp_desc_sc7280 },
176 { .compatible = "qcom,sc7280-edp", .data = &msm_dp_desc_sc7280 },
177 { .compatible = "qcom,sc8180x-dp", .data = &msm_dp_desc_sc8180x },
178 { .compatible = "qcom,sc8180x-edp", .data = &msm_dp_desc_sc8180x },
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/linux/drivers/gpu/drm/rockchip/
H A Danalogix_dp-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Author: Andy Yan <andy.yan@rock-chips.com>
7 * Yakir Yang <ykk@rock-chips.com>
8 * Jeff Chen <jeff.chen@rock-chips.com>
45 * struct rockchip_dp_chip_data - splite the grf setting of kind of chips
47 * @lcdsel_big: reg value of selecting vop big for eDP
48 * @lcdsel_lit: reg value of selecting vop little for eDP
89 reset_control_assert(dp->rst); in rockchip_dp_pre_init()
91 reset_control_deassert(dp->rst); in rockchip_dp_pre_init()
101 ret = clk_prepare_enable(dp->pclk); in rockchip_dp_poweron()
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/linux/include/drm/display/
H A Ddrm_dp_helper.h75 * struct drm_dp_vsc_sdp - drm DP VSC SDP
78 * It is based on DP 1.4 spec [Table 2-116: VSC SDP Header Bytes] and
79 * [Table 2-117: VSC SDP Payload for DB16 through DB18]
81 * @sdp_type: secondary-data packet type
88 * @content_type: CTA-861-G defines content types and expected processing by a sink device
102 * struct drm_dp_as_sdp - drm DP Adaptive Sync SDP
105 * It is based on DP 2.1 spec [Table 2-126: Adaptive-Sync SDP Header Bytes] and
106 * [Table 2-127: Adaptive-Sync SDP Payload for DB0 through DB8]
108 * @sdp_type: Secondary-data packet type
199 /* DP/eDP DSC support */
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/linux/Documentation/devicetree/bindings/display/
H A Ddp-aux-bus.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/dp-aux-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Douglas Anderson <dianders@chromium.org>
20 of the DP controller under the "aux-bus" node.
22 At the moment, this binding only handles the eDP case. It is
25 bus instead of a panel.
29 const: aux-bus
31 panel:
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/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8186-corsola-krabby.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
7 #include "mt8186-corsola.dtsi"
8 #include <dt-bindings/gpio/gpio.h>
17 remote-endpoint = <&ps8640_in>;
21 clock-frequency = <400000>;
23 edp-bridge@8 {
26 pinctrl-names = "default";
27 pinctrl-0 = <&ps8640_pins>;
28 powerdown-gpios = <&pio 96 GPIO_ACTIVE_LOW>;
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H A Dmt8186-corsola-steelix.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
7 #include "mt8186-corsola.dtsi"
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
12 pp1000_edpbrdg: regulator-pp1000-edpbrdg {
13 compatible = "regulator-fixed";
14 regulator-name = "pp1000_edpbrdg";
15 pinctrl-names = "default";
16 pinctrl-0 = <&en_pp1000_edpbrdg>;
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/linux/Documentation/devicetree/bindings/display/tegra/
H A Dnvidia,tegra124-sor.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124-sor.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The Serial Output Resource (SOR) can be used to drive HDMI, LVDS, eDP
19 pattern: "^sor@[0-9a-f]+$"
23 - enum:
24 - nvidia,tegra124-sor
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/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_psr.c35 struct dc *dc = link->ctx->dc; in link_supports_psrsu()
37 if (!dc->caps.dmcub_support) in link_supports_psrsu()
40 if (dc->ctx->dce_version < DCN_VERSION_3_1) in link_supports_psrsu()
46 if (!link->dpcd_caps.alpm_caps.bits.AUX_WAKE_ALPM_CAP || in link_supports_psrsu()
47 !link->dpcd_caps.psr_info.psr_dpcd_caps.bits.Y_COORDINATE_REQUIRED) in link_supports_psrsu()
50 if (link->dpcd_caps.psr_info.psr_dpcd_caps.bits.SU_GRANULARITY_REQUIRED && in link_supports_psrsu()
51 !link->dpcd_caps.psr_info.psr2_su_y_granularity_cap) in link_supports_psrsu()
57 /* Temporarily disable PSR-SU to avoid glitches */ in link_supports_psrsu()
62 * amdgpu_dm_set_psr_caps() - set link psr capabilities
68 if (!(link->connector_signal & SIGNAL_TYPE_EDP)) { in amdgpu_dm_set_psr_caps()
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